參數(shù)資料
型號: DS26503L+
廠商: Maxim Integrated Products
文件頁數(shù): 119/122頁
文件大?。?/td> 0K
描述: IC T1/E1/J1 BITS ELEMENT 64-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 160
類型: BITS 元件,多路復(fù)用器
PLL:
主要目的: T1/E1
輸入: 時(shí)鐘
輸出: 時(shí)鐘
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 無/無
頻率 - 最大: 6.312MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
產(chǎn)品目錄頁面: 1430 (CN2011-ZH PDF)
DS26503 T1/E1/J1 BITS Element
96 of 122
15. 6312kHz SYNCHRONIZATION INTERFACE
The DS26503 has a 6312kHz Synchronization Interface mode of operation that conforms with Appendix
II.2 of G.703, with the exception that the DS26503 transmits a square wave as opposed to the sine wave
that is defined in the G.703 specification.
15.1 Receive 6312kHz Synchronization Interface Operation
On the receive interface, a 6312kHz sine wave is accepted conforming to the input port requirements of
G.703 Appendix II. Alternatively, a 6312kHz square wave will also be accepted. A 6312kHz square wave
is output on RCLK in the receive direction. RS is not driven in this mode and will be three-stated.
Table 15-1. Specification of 6312kHz Clock
Signal at Input Port
Frequency
6312kHz
Signal format
Sinusoidal wave
Alarm condition
Alarm should not be occurred against
the amplitude ranged
-16dBm to +3dBm
15.2 Transmit 6312kHz Synchronization Interface Operation
On the transmit interface, a nominally 50% duty cycle, 6312kHz square wave at standard logic levels is
available from the PLL_OUT pin. In normal operation, the TCLKO pin will output the same signal.
However, if remote loopback is enabled then TCLKO will be replaced with the recovered receive clock.
See Figure 3-1. The G.703 requirements for the 6312kHz transmitted signal are shown in Table 15-2. The
user must provide an external circuit to convert the TCLKO or PLL_OUT signal to the level and
impedance required by G.703. The RSER and TS pins are ignored in this mode. TTIP and TRING will be
three-stated in this mode.
Table 15-2. Specification of 6312kHz Clock
Signal at Output Port
Frequency
6312kHz
Load impedance
75
Ω resistive
Transmission media
Coaxial pair cable
Amplitude
0dBm
± 3dBm
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