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參數(shù)資料
| 型號： | DS2450S+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 21/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CONVERTER A/D QUAD 1-W 8-SOIC |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 產(chǎn)品變化通告： | Product Discontinuation 27/Jul/12 |
| 標準包裝： | 2,000 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 1k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 2.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個單端，單極 |
DS2450
5 of 24
The next bits, OC (output control) and OE (enable output) control the alternate use of a channel as output.
For normal operation as analog input the OE bit of a channel needs to be 0, rendering the OC bit to a
don’t care. With OE set to 1, a 0 for OC will make the channel’s output transistor conducting, a 1 for OC
will switch the transistor off. With a pullup resistor to a positive voltage, for example, the OC bit will
directly translate into the voltage equivalent of its logic state. Enabling the output does not disable the
analog input. Conversions remain possible, but will result in values close to 0 if the transistor is
conducting.
The IR bit in the second byte of a channel’s control and status memory selects the input voltage range.
With IR set to 0, the highest possible conversion result is reached at 2.55V. Setting IR to 1 requires an
input voltage of 5.10V for the same result. The next bit beyond IR has no function. It will always read 0
and cannot be changed to 1.
The next two bits, AEL alarm enable low and AEH alarm enable high, control whether the device will
respond to the Conditional Search command (see ROM Functions) if a conversion results in a value
higher (AEH) than or lower (AEL) than the channel’s alarm threshold voltage as specified in the alarm
settings. The alarm flags AFL (low) and AFH (high) tell the bus master whether the channel’s input
voltage was beyond the low or high threshold at the latest conversion. These flags are cleared
automatically if a new conversion reveals a non-alarming value. They can alternatively be written to 0 by
the bus master without a conversion.
The next bit of a channel’s control and status memory always reads 0 and cannot be changed to 1. The
POR bit (power on reset) is automatically set to 1 as the device performs a power-on reset cycle. As long
as this bit is set the device will always respond to the Conditional Search command in order to notify the
bus master that the control and threshold data is no longer valid. After powering-up the POR bit needs to
be written to 0 by the bus master. This may be done together with restoring the control and threshold
data. It is possible for the bus master to write the POR bit to a 1. This will make the device participate in
the conditional search but will not generate a reset cycle. Since the POR bit is related to the device and
not channel-specific the value written with the most recent setting of an input range or alarm enable
applies. The power-on default setting for the control/status data is 08h for the first and 8Ch for the
second byte of each channel.
MEMORY MAP PAGE 1, CONTROL/STATUS DATA
Figure 5b
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
08
OE-A
OC-A
0
RC3-A
RC2-A
RC1-A
RC0-A
09
POR
0
AFH-A
AFL-A
AEH-A
AEL-A
0
IR-A
0A
OE-B
OC-B
0
RC3-B
RC2-B
RC1-B
RC0-B
0B
POR
0
AFH-B
AFL-B
AEH-B
AEL-B
0
IR-B
0C
OE-C
OC-C
0
RC3-C
RC2-C
RC1-C
RC0-C
0D
POR
0
AFH-C
AFL-C
AEH-C
AEL-C
0
IR-C
0E
OE-D
OC-D
0
RC3-D
RC2-D
RC1-D
RC0-D
0F
POR
0
AFH-D
AFL-D
AEH-D
AEL-D
0
IR-D
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