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參數(shù)資料
| 型號： | DS2450S+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 10/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CONVERTER A/D QUAD 1-W 8-SOIC |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 產品變化通告： | Product Discontinuation 27/Jul/12 |
| 標準包裝： | 2,000 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 1k |
| 數(shù)據(jù)接口： | 串行 |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 2.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.209"，5.30mm 寬） |
| 供應商設備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個單端，單極 |
DS2450
18 of 24
USAGE EXAMPLE (control channel A and channel B outputs)
MASTER MODE
DATA (LSB FIRST) COMMENTS
TX
Reset
Reset Pulse (480 - 960 μs)
RX
Presence
Presence Pulse
TX
CCh
Issue “Skip ROM” Command
TX
55h
Issue “Write Memory” Command
TX
08h
TA1, beginning address
TX
00h
TA2, address = 0008h
TX
80h if AFL = 1 / C0h if
AFL = 0
data byte (address 0008)
CH-A
RX
<CRC16>
CRC of command, address, data byte
RX
<data byte>
read-back for simple verification
TX
00h
next data byte (address 0009h)*
RX
<CRC16>
CRC of address, data byte
RX
00h
read-back for simple verification
TX
80h if AFH = 1 / C0h if
AFH = 0
data byte (address 000A)
CH-B
RX
<CRC16>
CRC of address, data byte
RX
<data byte>
read-back for simple verification
TX
Reset
Reset Pulse (480 - 960 μs)
RX
Presence
Presence Pulse
*In a multi-drop environment it takes less time to perform a non-changing write cycle rather than
skipping a byte.
1-WIRE SIGNALING
The DS2450 requires strict protocols to ensure data integrity. The protocol consists of four types of
signaling on one line: reset sequence with reset pulse and presence pulse, Write 0, Write 1 and Read Data.
All these signals except presence pulse are initiated by the bus master. The DS2450 can communicate at
two different speeds, regular speed and Overdrive Speed. If not explicitly set into the Overdrive mode,
the DS2450 will communicate at regular speed. While in Overdrive mode the fast timing applies to all
wave forms.
The initialization sequence required to begin any communication with the DS2450 is shown in Figure 10.
A Reset Pulse followed by a Presence Pulse indicates the DS2450 is ready to send or receive data given
the correct ROM command and memory function command. The bus master transmits (TX) a reset pulse
(tRSTL, minimum 480 μs at regular speed, 48 μs at Overdrive Speed). The bus master then releases the
line and goes into receive mode (RX). The 1-Wire bus is pulled to a high state via the pullup resistor.
After detecting the rising edge on the data pin, the DS2450 waits (tPDH,15-60 μs at regular speed, 2-6 μs
at Overdrive speed) and then transmits the Presence Pulse (tPDL, 60-240 μs at regular speed, 8-24 μs at
Overdrive Speed).
A Reset Pulse of 480 μs or longer will exit the Overdrive Mode returning the device to regular speed. If
the DS2450 is in Overdrive Mode and the Reset Pulse is no longer than 80 μs the device will remain in
Overdrive Mode.
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