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參數(shù)資料
| 型號： | DS2415X |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Timer or RTC |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, X6 |
| 封裝： | CHIP SCALE |
| 文件頁數(shù)： | 12/14頁 |
| 文件大?。?/td> | 343K |
| 代理商： | DS2415X |
DS2415
7 of 14
HARDWARE CONFIGURATION Figure 6
1-WIRE BUS SYSTEM
The 1-Wire bus is a system which has a single bus master and one or more slaves. In all instances the
DS2415 behaves as a slave. The discussion of this bus system is broken down into three topics: hardware
configuration, transaction sequence, and 1-Wire signaling (signal types and timing). A 1-Wire protocol
defines bus transactions in terms of the bus state during specified time slots that are initiated on the falling
edge of sync pulses from the bus master. For a more detailed protocol description, refer to Chapter 4 of
the Book of DS19xx iButton Standards.
Hardware Configuration
The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to
drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open
drain or 3-state outputs. The 1-Wire input of the DS2415 is open drain with an internal circuit equivalent
to that shown in Figure 6. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. The 1-
Wire bus has a maximum data rate of 16.3k bits per second and requires a pullup resistor of
approximately 5 k
.
The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus
MUST be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low
for more than 120
s, one or more of the devices on the bus may be reset. Since the DS2415 gets all its
energy for operation through its VBAT pin it will NOT perform a power-on reset if the 1-Wire bus is low
for an extended time period.
Transaction Sequence
The protocol for accessing the DS2415 via the 1-Wire port is as follows:
Initialization
ROM Function Command
Clock Function Command
INITIALIZATION
All transactions on the 1-ire bus begin with an initialization sequence. The initialization sequence consists
of a Reset Pulse transmitted by the bus master followed by Presence Pulse(s) transmitted by the slave(s).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS2417X | 0 TIMER(S), REAL TIME CLOCK, PBGA6 |
| DS2417P | 0 TIMER(S), REAL TIME CLOCK, PDSO6 |
| DS2422X | SPECIALTY MEMORY CIRCUIT, UUC |
| DS2423P/T&R | SPECIALTY MEMORY CIRCUIT, PDSO6 |
| DS2423P | SPECIALTY MEMORY CIRCUIT, PDSO6 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2416FP00K | 制造商:Thomas & Betts 功能描述:200A,CON,3P4W,MG,416,3P208V,CC |
| DS2416FR000 | 制造商:Thomas & Betts 功能描述:200A,REC,3P4W,MG,416,3P208V,SC |
| DS2416FRAB0 | 制造商:Thomas & Betts 功能描述:200A,REC.,3P4W,3PHASE,208V |
| DS2416MP000 | 制造商:Thomas & Betts 功能描述:DS2416MP000 200A,PLG,3P4W,MG,416 制造商:Thomas & Betts 功能描述:200A,PLG,3P4W,MG,416,3P208V |
| DS2416MP00K | 制造商:Thomas & Betts 功能描述:200A,PLG,3P4W,MG,416,3P208V,CC |
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