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參數(shù)資料
型號: DS2409P
廠商: Maxim Integrated Products
文件頁數(shù): 10/18頁
文件大?。?/td> 0K
描述: IC COUPLER MICROLAN 1-WIRE 6TSOC
標準包裝: 120
接口: 1 線
電源電壓: 4.5 V ~ 5.5 V
封裝/外殼: 6-LSOJ
供應商設備封裝: 6-TSOC
包裝: 管件
安裝類型: 表面貼裝
DS2409
18 of 18
AC ELECTRICAL CHARACTERISTICS
(-40°C to +85°C, VDD = 5V ±10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Time Slot
tSLOT
60
120
s
Write 1 Low Time
tLOW1
115
s
10
Write 0 Low Time
tLOW0
60
120
s
Read Low Time
tLOWR
115
s
10
Read Data Valid
tRDV
15
s
9
Release Time
tRELEASE
015
45
s
Read Data Setup
tSU
1s
6
Recovery Time
tREC
1s
Reset Time High
tRSTH
480
s
5
Reset Time Low
tRSTL
480
960
s
7
Presence Detect High
tPDH
15
60
s
Presence Detect Low
tPDL
60
240
s
NOTES:
1. All voltages are referenced to ground.
2. Measured with outputs open.
3. VPUP = external pullup voltage.
4. Input load is to ground.
5. An additional reset or communication sequence cannot begin until the reset high time has expired.
6. Read data setup time refers to the time the bus master must pull the I/O line low to read a bit. Data is
guaranteed to be valid within 1 s of this falling edge.
7. The reset low time (tRSTL) should be restricted to a maximum of 960 s, to allow interrupt signaling,
otherwise, it could mask or conceal interrupt pulses. The DS2409 may perform a power-on reset cycle
and deactivate both 1-Wire outputs if the 1-Wire input is low for minimum 8 ms. A low time of 12 ms
or more will always cause a power-on reset cycle.
8. The main output has a slew rate controlled output. The indicated current is a DC value. The sink
current typically reaches 80% of its DC value 1 s after turning on the transistor.
9. The optimal sampling point for the master is as close as possible to the end time of the 15s tRDV
period without exceeding tRDV. For the case of a Read-One Time Slot, this maximizes the amount of
time for the pull-up resistor to recover to a high level. For a Read-Zero Time Slot, it ensures that a
read will occur before the fastest 1-Wire device(s) release the line.
10. The duration of the low pulse sent by the master should be a minimum of 1s with a maximum value
as short as possible to allow time for the pull-up resistor to recover the line to a high level before the
1-Wire device samples in the case of a Write-One Time or before the master samples in the case of a
Read-One Time.
Not
Recommended
for
New
Design
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