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參數(shù)資料
| 型號： | DS2406P+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 24/32頁 |
| 文件大小： | 0K |
| 描述： | IC SW DL ADDRESS W/1K MEM 6-TSOC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 4,000 |
| 應(yīng)用： | 遙控，遙測 |
| 接口： | 1 線 |
| 電源電壓： | 2.8 V ~ 6 V |
| 封裝/外殼： | 6-LSOJ |
| 供應(yīng)商設(shè)備封裝： | 6-TSOC |
| 包裝： | 帶卷 (TR) |
| 安裝類型： | 表面貼裝 |
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DS2406
30 of 32
PIO SINK CURRENT
10 mA
20 mA
30 mA
40 mA
50 mA
60 mA
70 mA
80 mA
90 mA
100 mA
I SA , I SB
@ 0.4V
VPUP
PIO-B
max.
min.
PIO-A
max.
min.
4V
5V
6V
2.8V
NOTE: The sink current is production-tested at VPUP = 2.8V; the specification for VPUP of 4V, 5V and
6V is guaranteed by design.
NOTES:
1. All voltages are referenced to ground.
2. VPUP, VPUPA, VPUPB = external pull-up voltage.
3. VIH is a function of the chip-internal supply voltage. This voltage is determined by either the external
pull-up resistor and VPUP or the VCC supply, whichever is higher. Without VCC supply, VIH for either
PIO pin should always be greater than or equal to VPUP -0.3V.
4. Input load is to ground.
5. Leakage current is to ground.
6. Guaranteed by design, not production tested.
7. If the current at PIO-A reaches 200mA the gate voltage of the output transistor will be reduced to
limit the sink current to 200mA. The user-supplied circuitry should limit the current flow through the
PIO-transistor to no more than 100mA. Otherwise the DS2406 may be damaged.
8. PIO-A has a controlled turn-on output. The indicated currents are DC values. At VPUP = 4.0V or
higher the sink current typically reaches 80% of its DC value 1 s after turning on the transistor.
9. VCC must be at least 4.0V if it is to be connected during a programming pulse.
10. Capacitance on the data pin could be 800pF when power is first applied. If a 5k
Ω resistor is used to
pull up the data line to VPUP, 5s after power has been applied the parasite capacitance will not affect
normal communications.
11. The duration of the low pulse sent by the master should be a minimum of 2s with a maximum value
as short as possible to allow time for the pull-up resistor to recover the line to a high level before the
1-Wire device samples in the case of a Write 1 Low Time, or before the master samples in the case of
a Read Low Time.
12. The optimal sampling point for the master is as close as possible to the end time of the 15
μs tRDV
period without exceeding tRDV. For the case of a Read-one time slot, this maximizes the amount of
time for the pull-up resistor to recover the line to a high level. For a Read-zero time slot it ensures
that a read will occur before the fastest 1-Wire devices(s) release the line (tRELEASE = 0).
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