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參數(shù)資料
| 型號： | DS21Q59LN+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 35/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX E1 QUAD 100-LQFP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 90 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 4/4 |
| 規(guī)程： | E1 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
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DS21Q59 Quad E1 Transceiver
40 of 76
14.
SYSTEM CLOCK INTERFACE
A single system clock interface (SCI) is common to all four DS21Q59 transceivers. The SCI is designed to allow
any one of the four receivers to act as the master reference clock for the system. When multiple DS21Q59s are
used to build an N port system, the SCI allows any one of the N ports to be the master. The selected reference is
then distributed to the other DS21Q59s through the REFCLK pin. The REFCLK pin acts as an output on the
DS21Q59, which has been selected to provide the reference clock from one of its four receivers. On DS21Q59s not
selected to source the reference clock, this pin becomes an input by writing 0s to the SCSx bits. The reference
clock is also passed to the clock synthesizer PLL to generate a 2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz
clock. This clock can then be used with the IBO function to merge up to eight E1 lines onto a single high-speed
PCM bus. In the event that the master E1 port fails (enters a receive carrier loss condition), that port automatically
switches to the clock present on the MCLK pin. Therefore, MCLK acts as the backup source of master clock. The
host can then find and select a functioning E1 port as the master. Because the selected port’s clock is passed to
the other DS21Q59s in a multiple device configuration, one DS21Q59’s synthesizer can always be the source of
the high-speed clock. This allows smooth transitions when clock-source switching occurs. The SCI control register
exists in Transceiver 1 only (TS0, TS1 = 0).
Register Name:
SCICR
Register Description:
System Clock Interface Control Register
(Note: This register is valid only for Transceiver 1 (TS0 = 0, TS1 = 0).)
Register Address:
1D Hex
Bit #
7
6
5
4
3
2
1
0
Name
AJACKE
BUCS
SOE
CSS1
CSS0
SCS2
SCS1
SCS0
NAME
BIT
FUNCTION
AJACKE
7
AJACK Enable. This bit enables the alternate jitter attenuator.
BUCS
6
Backup Clock Select. Selects which clock source to switch to
automatically during a loss-of-transmit clock event.
0 = during an LOTC event switch to MCLK
1 = during an LOTC event switch to system reference clock
SOE
5
Synthesizer Output Enable
0 = 2/4/8/16MCK pin in high-Z mode
1 = 2/4/8/16MCK pin active
CSS1
4
Clock Synthesizer Select Bit 1 (Table 14-A)
CSS0
3
Clock Synthesizer Select Bit 0 (Table 14-A)
SCS2
2
System Clock Select Bit 2 (Table 14-B)
SCS1
1
System Clock Select Bit 1 (Table 14-B)
SCS0
0
System Clock Select Bit 0 (Table 14-B)
Table 14-A. Synthesizer Output Select
CSS1
CSS0
SYNTHESIZER OUTPUT
FREQUENCY (MHz)
0
2.048
0
1
4.096
1
0
8.192
1
16.384
Table 14-B. System Clock Selection
SCS2
SCS1
SCS0
PORT SELECTED AS MASTER
0
None (Master Port can be derived from another DS21Q59 in the system.)
0
1
Transceiver 1
0
1
0
Transceiver 2
0
1
Transceiver 3
1
0
Transceiver 4
1
0
1
Reserved for future use.
1
0
Reserved for future use.
1
Reserved for future use.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21Q59LN+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21S07A | 制造商:Maxim Integrated Products 功能描述: |
| DS21S07AE | 功能描述:SCSI 接口集成電路 RoHS:否 制造商:Texas Instruments 工作電源電壓:2.7 V to 5.25 V 電源電流:13 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 安裝風格:SMD/SMT 封裝 / 箱體:SSOP-36 封裝:Tube |
| DS21S07AE/T | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:SCSI Terminator |
| DS21S07AE/T&R | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: 制造商:Maxim Integrated Products 功能描述:IC TERMINATOR SCSI 20-TSSOP |
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