15
參數(shù)資料
型號(hào)： DS21Q59LN+
廠商： Maxim Integrated Products
文件頁數(shù)： 33/76頁
文件大?。?/td> 0K
描述： IC TXRX E1 QUAD 100-LQFP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 90
類型： 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù)： 4/4
規(guī)程： E1
電源電壓： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-LQFP（14x14）
包裝： 托盤
DS21Q59 Quad E1 Transceiver
39 of 76
13.
PRBS GENERATION AND DETECTION
The DS21Q59 can transmit and receive the 2
15 - 1 PRBS pattern. This PRBS pattern complies with ITU-T O.151
specifications. The PRBS pattern can be unframed (in all 256 bits of the frame), framed (in all time slots except
TS0), or in any single time slot. Register CCR5 contains the control bits for configuring the transmit and receives
PRBS functions. See Table 13-A and Table 13-B for selecting the transmit and receive modes of operation. In
transmit and receive mode 1 operation, the transmit- and receive-channel monitor-select bits of registers CCR3
and CCR4 have an alternate use. When this mode is selected, these bits determine which time slot transmits
and/or receives the PRBS pattern.
SR2.0 indicates when the receiver has synchronized to the PRBS pattern. The PRBS synchronizer remains in sync
until it experiences six or more bit errors within a 64-bit span. Choosing any receive mode other than NORMAL
causes the 16-bit E-bit error counter—EBCR1 and EBCR2—to be reconfigured for counting PRBS errors.
User-definable outputs OUTA or OUTB can be configured to output a pulse for every bit error received. See
Section 20 and Table 20-A for details. This signal can be used with external circuitry to keep track of bit-error rates
during PRBS testing. Once synchronized, any bit errors received cause a positive-going pulse, synchronous with
RCLK.
Table 13-A. Transmit PRBS Mode Select
TPRBS1
(CCR5.3)
TPBRS0
(CCR5.2)
MODE
0
Mode 0: Normal (PRBS disabled)
0
1
Mode 1: PRBS in TSx. PRBS pattern is transmitted in a single time slot (TS). In this mode, the
transmit-channel monitor-select bits in register CCR3 are used to select a time slot in which to
transmit the PRBS pattern.
1
0
Mode 2: PRBS in all but TS0. PRBS pattern is transmitted in time slots 1 through 31.
1
Mode 3: PRBS unframed. PRBS pattern is transmitted in all time slots.
Table 13-B. Receive PRBS Mode Select
RPRBS1
(CCR5.1)
RPBRS0
(CCR5.0)
MODE
0
Mode 0: Normal (PRBS disabled)
0
1
Mode 1: PRBS in TSx. PRBS pattern is received in a single time slot (TS). In this mode, the
receive-channel monitor-select bits in register CCR4 are used to select a time slot in which to
receive the PRBS pattern.
1
0
Mode 2: PRBS in all but TS0. PRBS pattern is received in time slots 1 through 31.
1
Mode 3: PRBS unframed. PRBS pattern is received in all time slots.
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