參數(shù)資料
型號： DS21Q59DK
廠商： Maxim Integrated Products
文件頁數(shù)： 22/76頁
文件大?。?/td> 0K
描述： KIT DESIGN FOR DS21Q59
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 1
主要目的： 電信，調幀器和線路接口裝置（LIU）
已用 IC / 零件： DS21Q59
DS21Q59 Quad E1 Transceiver
29 of 76
Register Name:
SSR
Register Description:
Synchronizer Status Register
Register Address:
09 Hex
Bit #
7
6
5
4
3
2
1
0
Name
CSC5
CSC4
CSC3
CSC2
CSC0
FASSA
CASSA
CRC4SA
NAME
BIT
FUNCTION
CSC5
7
CRC4 Sync Counter Bit 5. MSB of the 6-bit counter.
CSC4
6
CRC4 Sync Counter Bit 4
CSC3
5
CRC4 Sync Counter Bit 3
CSC2
4
CRC4 Sync Counter Bit 2
CSC0
3
CRC4 Sync Counter Bit 0. LSB of the 6-bit counter. Counter bit 1 is not
accessible.
FASSA
2
FAS Sync Active. Set while the synchronizer is searching for alignment at the
FAS level.
CASSA
1
CAS MF Sync Active. Set while the synchronizer is searching for the CAS MF
alignment word.
CRC4SA
0
CRC4 MF Sync Active. Set while the synchronizer is searching for the CRC4
MF alignment word.
9.2 CRC4 Sync Counter
The CRC4 sync counter increments each time the 8ms CRC4 multiframe search times out. The counter is cleared
when the framer has successfully obtained synchronization at the CRC4 level. The counter can also be cleared by
disabling the CRC4 mode (CCR1.0 = 0). This counter is useful for determining the amount of time the framer has
been searching for synchronization at the CRC4 level. ITU G.706 suggests that if synchronization at the CRC4
level cannot be obtained within 400ms, the search should be abandoned and proper action taken. The CRC4 sync
counter rolls over.
Table 9-A. Alarm Criteria
ALARM
SET CRITERIA
CLEAR CRITERIA
ITU SPEC
RSA1
(Receive Signaling
All Ones)
Over 16 consecutive frames (one full
MF) time slot 16 contains less than three
zeros
Over 16 consecutive frames (one full
MF) time slot 16 contains three or more
zeros
G.732
4.2
RSA0
(Receive Signaling
All Zeros)
Over 16 consecutive frames (one full
MF) time slot 16 contains all zeros
Over 16 consecutive frames (one full
MF) time slot 16 contains at least a
single one
G.732
5.2
RDMA
(Receive Distant
Multiframe Alarm)
Bit 6 in time slot 16 of frame 0 set to one
for two consecutive MF
Bit 6 in time slot 16 of frame 0 set to
zero for two consecutive MF
O.162
2.1.5
RUA1
(Receive Unframed
All Ones)
Fewer than three zeros in two frames
(512 bits)
More than two zeros in two frames (512
bits)
O.162
1.6.1.2
RRA
(Receive Remote
Alarm)
Bit 3 of nonalign frame set to one for
three consecutive occasions
Bit 3 of nonalign frame set to zero for
three consecutive occasions
O.162
2.1.4
RCL
(Receive Carrier
Loss)
255 (or 2048) consecutive zeros
received
In 255-bit times at least 32 ones are
received
G.775/
G.962
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DS21Q59L 功能描述:網(wǎng)絡控制器與處理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21Q59L+ 功能描述:網(wǎng)絡控制器與處理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21Q59LN 功能描述:網(wǎng)絡控制器與處理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21Q59LN+ 功能描述:網(wǎng)絡控制器與處理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21S07A 制造商:Maxim Integrated Products 功能描述:
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