參數(shù)資料
型號(hào)： DS21Q59DK
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 11/76頁(yè)
文件大?。?/td> 0K
描述： KIT DESIGN FOR DS21Q59
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
主要目的： 電信，調(diào)幀器和線路接口裝置（LIU）
已用 IC / 零件： DS21Q59
DS21Q59 Quad E1 Transceiver
19 of 76
Table 8-A. Sync/Resync Criteria
FRAME OR
MULTIFRAME
LEVEL
SYNC CRITERIA
RESYNC CRITERIA
ITU SPEC.
FAS
FAS present in frame N and N + 2,
and FAS not present in frame N + 1
Three consecutive incorrect FAS received;
alternate (RCR1.2 = 1): if the above criteria
is met or three consecutive incorrect bit 2 of
non-FAS received
G.706
4.1.1
4.1.2
CRC4
Two valid MF alignment words found
within 8ms
915 or more CRC4 codewords out of 1000
received in error
G.706
4.2 and 4.3.2
CAS
Valid MF alignment word found and
previous time slot 16 contains code
other than all zeros
Two consecutive MF alignment words
received in error
G.732 5.2
Register Name:
TCR
Register Description:
Transmit Control Register
Register Address:
11 Hex
Bit #
7
6
5
4
3
2
1
0
Name
IFSS
TFPT
AEBE
TUA1
TSiS
TSA1
TSM
TSIO
NAME
BIT
FUNCTION
IFSS
7
Internal Frame-Sync Select
0 = TSYNC normal
1 = if TSYNC is in the INPUT mode (TSIO = 0), then TSYNC is internally
replaced by the recovered receive frame sync. The TSYNC pin is ignored
1 = if TSYNC is in the OUTPUT mode (TSIO = 1), then TSYNC outputs the
recovered multiframe frame sync
TFPT
6
Transmit Time Slot 0 Pass Through
0 = FAS bits/Sa bits/remote alarm sourced internally from the TAF and TNAF
registers
1 = FAS bits/Sa bits/remote alarm sourced from TSER
AEBE
5
Automatic E-Bit Enable
0 = E-bits not automatically set in the transmit direction
1 = E-bits automatically set in the transmit direction
TUA1
4
Transmit Unframed All Ones
0 = transmit data normally
1 = transmit an unframed all-ones code
TSiS
3
Transmit International Bit Select
0 = sample Si bits at TSER pin
1 = source Si bits from TAF and TNAF registers (In this mode, TCR.6 must be
set to 0)
TSA1
2
Transmit Signaling All Ones
0 = normal operation
1 = force time slot 16 in every frame to all ones
TSM
1
TSYNC Mode Select
0 = frame mode (see the timing diagrams in Section 24.2)
1 = CAS and CRC4 multiframe mode (see the timing diagrams in Section 24.2)
TSIO
0
TSYNC I/O Select
0 = TSYNC is an input
1 = TSYNC is an output
Note: See Figure 24-9 for more details about how the transmit control register affects DS21Q59 operation.
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DS21Q59LN 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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DS21S07A 制造商:Maxim Integrated Products 功能描述:
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