- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10992 > DS21Q50LN+ (Maxim Integrated Products)IC TXRX E1 QUAD 100-LQFP PDF資料下載
參數(shù)資料
| 型號： | DS21Q50LN+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 52/87頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX E1 QUAD 100-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 90 |
| 功能： | 收發(fā)器 |
| 接口： | E1 |
| 電路數(shù)： | 4 |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 電流 - 電源： | 230mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
| 包括： | AIS 警報檢測器和發(fā)生器，回送功能，PRBS 發(fā)生器 / 檢測器，遠程檢測器和發(fā)生器 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁當前第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁
DS21Q50
56 of 87
16.
LINE INTERFACE UNIT
The line interface unit in the DS21Q50 contains three sections: the receiver, which handles clock and data
recovery; the transmitter, which waveshapes and drives the E1 line; and the jitter attenuator. The line
interface control register (LICR), described below, controls each of these three sections.
Register Name:
LICR
Register Description:
Line Interface Control Register
Register Address:
17 Hex
Bit
7
6
5
4
3
2
1
0
Name
L2
L1
L0
EGL
JAS
JABDS
DJA
TPD
NAME
BIT
FUNCTION
L2
7
Line Build-Out Select Bit 2. Sets the transmitter build-out.
L1
6
Line Build-Out Select Bit 1. Sets the transmitter build-out.
L0
5
Line Build-Out Select Bit 0. Sets the transmitter build-out.
EGL
4
Receive Equalizer Gain Limit
0 = -12dB
1 = -43dB
JAS
3
Jitter Attenuator Select
0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
JABDS
2
Jitter Attenuator Buffer Depth Select
0 = 128 bits
1 = 32 bits (use for delay sensitive applications)
DJA
1
Disable Jitter Attenuator
0 = jitter attenuator enabled
1 = jitter attenuator disabled
TPD
0
Transmit Power-Down
0 = powers down the transmitter and three-states the TTIP and TRING pins
1 = normal transmitter operation
16.1 Receive Clock and Data Recovery
The DS21Q50 contains a digital clock-recovery system. See Figure 1-1 and Figure 16-2 for more details.
The device couples to the receive E1 shielded twisted pair or coax through a 1:1 transformer
(Table 16-4). The 2.048MHz clock attached at the MCLK pin is internally multiplied by 16 through an
internal PLL and fed to the clock recovery system. The clock recovery system uses the clock from the
PLL circuit to form a 16 times oversampler, which is used to recover the clock and data. This over-
sampling technique offers outstanding jitter tolerance (Figure 16-5).
Normally, RCLK is the recovered clock from the E1 AMI/HDB3 waveform presented at the RTIP and
RRING inputs. When no AMI signal is present at RTIP and RRING, a receive carrier loss (RCL)
condition occurs, and the RCLK is sourced from the clock applied at the MCLK pin. If the jitter
attenuator is either placed in the transmit path or is disabled, RCLK can exhibit slightly shorter high
cycles of the clock. This is because of the highly oversampled digital clock-recovery circuitry. If the jitter
attenuator is placed in the receive path (as is the case in most applications), the jitter attenuator restores
the RCLK to being close to 50% duty cycle. See the Receive AC Characteristics in Section 21.4 for more
details.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS21Q50L-W+ | TXRX E1 QUAD CLK/DATA 100LQFP |
| DS21Q50L+ | IC TXRX E1 QUAD 100-LQFP |
| DS3171N+ | TXRX SGL DS3/E3 400PBGA |
| DS2151QNB | IC TXRX T1 1-CH 5V LP IND 44PLCC |
| VI-B0Z-IY-F1 | CONVERTER MOD DC/DC 2V 20W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21Q50LN+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q50L-W+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q50N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| DS21Q55 | 功能描述:IC TXRX QUAD T1/E1/J1 SCT 256BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標準包裝:750 系列:* |
| DS21Q552 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V Quad T1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。