The DS21Q50 can transmit and receive the 215
參數(shù)資料
型號： DS21Q50L-W+
廠商： Maxim Integrated Products
文件頁數(shù)： 40/87頁
文件大?。?/td> 0K
描述： TXRX E1 QUAD CLK/DATA 100LQFP
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 90
功能： 收發(fā)器
接口： E1
電路數(shù)： 4
電源電壓： 3.14 V ~ 3.47 V
電流 - 電源： 230mA
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應商設備封裝： 100-LQFP（14x14）
包裝： 托盤
包括： *
其它名稱： 90-21Q50+LW0
DS21Q50
45 of 87
8. PRBS GENERATION AND DETECTION
The DS21Q50 can transmit and receive the 215 - 1 PRBS pattern. This PRBS pattern complies with ITU-
T O.151 specifications. The PRBS pattern can be unframed (in all 256 bits of the frame), framed (in all
time slots except TS0), or in any single time slot. Register CCR5 contains the control bits for configuring
the transmit and receive PRBS functions. Table 8-1 and Table 8-2 show the selection criteria for transmit
and receive operation modes. In transmit and receive mode 1 operation, the transmit and receive channel-
monitor select bits of registers CCR3 and CCR4 have an alternate use. When these modes are selected,
those bits determine which time slots transmit and/or receive the PRBS pattern.
SR2.0 indicates when the receiver has synchronized to the PRBS pattern. The PRBS synchronizer
remains in sync until it experiences 6-bit errors or more within a 64-bit span. Choosing any receive mode
other than NORMAL causes the 16-bit E-bit error counter—EBCR1 and EBCR2—to be reconfigured for
counting PRBS errors.
User-definable outputs OUTA or OUTB can be configured to output a pulse for every bit error received.
See Section 15 and Table 15-1 for details. This signal can be used with external circuitry to track bit error
rates during PRBS testing. Once synchronized, any bit errors received cause a positive-going pulse,
synchronous with RCLK.
Table 8-1. Transmit PRBS Mode Select
TPRBS1
(CCR5.3)
TPBRS0
(CCR5.2)
MODE
0
Mode 0: Normal (PRBS disabled)
0
1
Mode 1: PRBS in TSx. PRBS pattern is transmitted in a single time slot
(TS). In this mode, the transmit channel-monitor select bits in register
CCR3 are used to select a time slot in which to transmit the PRBS
pattern.
1
0
Mode 2: PRBS in all but TS0. PRBS pattern is transmitted in time slots 1
through 31.
1
Mode 3: PRBS unframed. PRBS pattern is transmitted in all time slots.
Table 8-2. Receive PRBS Mode Select
RPRBS1
(CCR5.1)
RPBRS0
(CCR5.0)
MODE
0
Mode 0: Normal (PRBS disabled)
0
1
Mode 1: PRBS in TSx. PRBS pattern is received in a single time slot
(TS). In this mode, the receive channel-monitor select bits in register
CCR4 are used to select a time slot in which to receive the PRBS pattern.
1
0
Mode 2: PRBS in all but TS0. PRBS pattern is received in time slots 1
through 31.
1
Mode 3: PRBS unframed. PRBS pattern is received in all time slots.
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