參數(shù)資料
型號(hào)： DS21Q50L-W+
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 28/87頁(yè)
文件大?。?/td> 0K
描述： TXRX E1 QUAD CLK/DATA 100LQFP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 90
功能： 收發(fā)器
接口： E1
電路數(shù)： 4
電源電壓： 3.14 V ~ 3.47 V
電流 - 電源： 230mA
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-LQFP（14x14）
包裝： 托盤
包括： *
其它名稱： 90-21Q50+LW0
DS21Q50
34 of 87
Register Name:
SSR
Register Description:
Synchronizer Status Register
Register Address:
09 Hex
Bit
7
6
5
4
3
2
1
0
Name
CSC5
CSC4
CSC3
CSC2
CSC0
FASSA
CASSA
CRC4SA
NAME
BIT
FUNCTION
CSC5
7
CRC4 Sync Counter Bit 5. MSB of the 6-bit counter.
CSC4
6
CRC4 Sync Counter Bit 4
CSC3
5
CRC4 Sync Counter Bit 3
CSC2
4
CRC4 Sync Counter Bit 2
CSC0
3
CRC4 Sync Counter Bit 0. LSB of the 6-bit counter. Counter Bit 1 is not accessible.
FASSA
2
FAS Sync Active. Set while the synchronizer is searching for alignment at the FAS level.
CASSA
1
CAS MF Sync Active. Set while the synchronizer is searching for the CAS MF alignment
word.
CRC4SA
0
CRC4 MF Sync Active. Set while the synchronizer is searching for the CRC4 MF
alignment word.
5.1 CRC4 Sync Counter
The CRC4 sync counter increments each time the 8ms CRC4 multiframe search times out. The counter is
cleared when the framer has successfully obtained synchronization at the CRC4 level. Disabling the
CRC4 mode (CCR1.0 = 0) can also clear the counter. This counter determines the time the framer has
been searching for synchronization at the CRC4 level. ITU G.706 suggests that if synchronization at the
CRC4 level cannot be obtained within 400ms, the search should be abandoned and proper action taken.
The CRC4 sync counter rolls over.
Table 5-1. Alarm Criteria
ALARM
SET CRITERIA
CLEAR CRITERIA
ITU SPEC
RSA1
(receive signaling
all ones)
Over 16 consecutive frames (one
full MF) time slot 16 contains
fewer than three 0s
Over 16 consecutive frames (one full
MF) time slot 16 contains three or
more 0s
G.732
4.2
RSA0
(receive signaling
all zeros)
Over 16 consecutive frames (one
full MF) time slot 16 contains all
0s
Over 16 consecutive frames (one full
MF) time slot 16 contains at least a
single 1
G.732
5.2
RDMA
(receive distant
multiframe alarm)
Bit 6 in time slot 16 of frame 0 set
to one for two consecutive MF
Bit 6 in time slot 16 of frame 0 set to 0
for two consecutive MF
O.162
2.1.5
RUA1
(receive unframed
all ones)
Fewer than three 0s in two frames
(512 bits)
More than two 0s in two frames (512
bits)
O.162
1.6.1.2
RRA
(receive remote
alarm)
Bit 3 of nonalign frame set to 1 for
three consecutive occasions
Bit 3 of nonalign frame set to 0 for
three consecutive occasions
O.162
2.1.4
RCL
(receive carrier loss)
255 (or 2048) consecutive 0s
received
In 255-bit times, at least 32 1s are
received
G.775/
G.962
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