參數資料
型號: DS21Q41BT
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PQFP128
封裝: TQFP-128
文件頁數: 60/61頁
文件大?。?/td> 714K
代理商: DS21Q41BT
DS21Q41B
8 of 61
DS21Q41B PIN DESCRIPTION Table 1-4
Transmit Clock [TCLK]. 1.544 MHz primary clock. Used to clock data through the transmit side
formatter.
Transmit Serial Data [TSER]. Transmit NRZ serial data. Sampled on the falling edge of TCLK when
the transmit side elastic store is disabled. Sampled on the falling edge of TSYSCLK when the transmit
side elastic store is enabled.
Transmit Channel Clock [TCHCLK]. 192 kHz clock which pulses high during the LSB of each
channel. Synchronous with TCLK when the transmit side elastic store is disabled. Synchronous with
TSYSCLK when the transmit side elastic store is enabled. Useful for parallel to serial conversion of
channel data, locating robbed-bit signaling bits, and for blocking clocks in DDS applications. See Section
12 for timing details.
Transmit Bipolar Data [TPOS and TNEG]. Updated on rising edge of TCLK. Can be programmed to
output NRZ data on TPOS via the TCR1.7 control bit.
Transmit Channel Block [TCHBLK]. A user programmable output that can be forced high or low
during any of the 24 T1 channels. Synchronous with TCLK when the transmit side elastic store is
disabled. Synchronous with TSYSCLK when the transmit side elastic store is enabled. Useful for
blocking clocks to a serial UART or LAPD controller in applications where not all T1 channels are used
such as Fractional T1, 384k bps service, 768k bps, or ISDN-PRI. Also useful for locating individual
channels in drop-and-insert applications and for per-channel loopback. See Section 12 for timing details.
Transmit System Clock [TSYSCLK]. 1.544 MHz or 2.048 MHz clock. Only used when the transmit
side elastic store function is enabled. Should be tied low in applications that do not use the transmit side
elastic store.
Transmit Link Clock [TLCLK]. 4 kHz or 2 kHz (ZBTSI) demand clock for the TLINK input. See
Section 12 for timing details.
Transmit Link Data [TLINK]. If enabled via TCR1.2, this pin will be sampled during the F-bit time on
the falling edge of TCLK for data insertion into either the FDL stream (ESF) or the Fs bit position (D4)
or the Z-bit position (ZBTSI). See Section 12 for timing details.
Transmit Sync [TSYNC]. A pulse at this pin will establish either frame or multiframe boundaries for the
DS21Q41B. Via TCR2.2, the DS21Q41B can be programmed to output either a frame or multiframe
pulse at this pin. If this pin is set to output pulses at frame boundaries, it can also be set via TCR2.4 to
output double-wide pulses at signaling frames. See Section 12 for timing details.
Transmit Frame Sync [TFSYNC]. 8 kHz pulse. Only used when the transmit side elastic store is
enabled. A pulse at this pin will establish frame boundaries for the DS21Q41B. Should be tied low in
applications that do not use the transmit side elastic store. See Section 12 for timing details.
Receive Link Data [RLINK]. Updated with either FDL data (ESF) or Fs bits (D4) or Z bits (ZBTSI) one
RCLK before the start of a frame. See Section 12 for timing details.
Receive Link Clock [RLCLK]. 4 kHz or 2 kHz (ZBTSI) demand clock for the RLINK input. See
Section 12 for timing details.
相關PDF資料
PDF描述
DS21Q42TN DATACOM, FRAMER, PQFP128
DS21Q42T DATACOM, FRAMER, PQFP128
DS21Q43AT DATACOM, FRAMER, PQFP128
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相關代理商/技術參數
參數描述
DS21Q41-BT 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述:
DS21Q41BT+ 功能描述:網絡控制器與處理器 IC RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21Q41BT+T 功能描述:網絡控制器與處理器 IC RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21Q41BTN 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Quad T1 Framer
DS21Q41-BTN 功能描述:網絡控制器與處理器 IC RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray