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參數(shù)資料
| 型號(hào)： | DS21Q41BT |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Digital Transmission Controller |
| 英文描述： | DATACOM, FRAMER, PQFP128 |
| 封裝： | TQFP-128 |
| 文件頁數(shù)： | 26/61頁 |
| 文件大?。?/td> | 714K |
| 代理商： | DS21Q41BT |
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DS21Q41B
32 of 61
MOSCR1:
MULTIFRAMES OUT OF SYNC COUNT REGISTER 1 (Address=25 Hex)
MOSCR2:
MULTIFRAMES OUT OF SYNC COUNT REGISTER 2 (Address=27 Hex)
(MSB)
(LSB)
MOS/FB11
MOS/FB10
MOS/FB9
MOS/FB8
(note 1)
MOSCR1
MOS/FB7
MOS/FB6
MOS/FB5
MOS/FB4
MOS/FB3
MOS/FB2
MOS/FB1
MOS/FB0
MOSCR2
SYMBOL
POSITION
NAME AND DESCRIPTION
MOS/FB11
MOSCR1.7
MSB of the 12-Bit multiframes out of sync or F-bit error count
(note 2)
MOS/FB0
MOSCR2.0
LSB of the 12-bit multiframes out of sync or F-bit error count
(note 2)
NOTES:
1. The lower nibble of the counter at address 25 is used by the Path Code Violation Count Register.
2. MOSCR counts either errors in framing bit position (RCR2.0=0) or the number of multiframes out of
sync (RCR2.0=1).
MULTIFRAMES OUT OF SYNC COUNTING ARRANGEMENTS Table 5-3
FRAMING MODE
(CCR2.3)
COUNT MOS OR F-BIT
ERRORS? (RCR2.0)
WHAT IS COUNTED IN THE MOSCRs
D4
MOS
number of multiframes out of sync
D4
F-BIT
errors in the Ft pattern
ESF
MOS
number of multiframes out of sync
ESF
F-BIT
errors in the FPS pattern
6.0 FDL/Fs EXTRACTION AND INSERTION
The DS21Q41B has the ability to extract/insert data from/into the Facility Data Link (FDL) in the ESF
framing mode and from/into Fs bit position in the D4 framing mode. Since SLC-96 utilizes the Fs bit
position, this capability can also be used in SLC-96 applications. The operation of the receive and
transmit sections will be discussed separately. Contact the factory for a copy of C language source code
for implementing the FDL on the DS21Q41B.
6.1 Receive Section
In the receive section, the recovered FDL bits or Fs bits are shifted bit-by-bit into the Receive FDL
register (RFDL). Since the RFDL is 8 bits in length, it will fill up every 2 ms (8 times 250
s). The
DS21Q41B will signal an external microcontroller that the buffer has filled via the SR2.4 bit. If enabled
via IMR2.4, the INT pin will toggle low indicating that the buffer has filled and needs to be read. The
user has 2 ms to read this data before it is lost. If the byte in the RFDL matches either of the bytes
programmed into the RFDLM1 or RFDLM2 registers, then the SR2.2 bit will be set to a 1 and the INT
pin will toggled low if enabled via IMR2.2. This feature allows an external microcontroller to ignore the
FDL or Fs pattern until an important event occurs.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS21Q42TN | DATACOM, FRAMER, PQFP128 |
| DS21Q42T | DATACOM, FRAMER, PQFP128 |
| DS21Q43AT | DATACOM, FRAMER, PQFP128 |
| DS21Q44T | DATACOM, FRAMER, PQFP128 |
| DS21Q44TN | DATACOM, FRAMER, PQFP128 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21Q41-BT | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| DS21Q41BT+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q41BT+T | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q41BTN | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Quad T1 Framer |
| DS21Q41-BTN | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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