參數(shù)資料
型號: DS21FT40
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA300
封裝: BGA-300
文件頁數(shù): 54/87頁
文件大?。?/td> 386K
代理商: DS21FT40
DS21FT40
58 of 87
Transmit a HDLC Message
1. Make sure HDLC controller is done sending any previous messages and is current sending flags by
checking that the FIFO is empty by reading the TEMPTY status bit in the THIR register.
2. Enable either the THALF or TNF interrupt.
3. Read THIR to obtain TFULL status.
A. If TFULL=0, then write a byte into the FIFO and skip to next step (special case occurs when
the last byte is to be written, in this case set TEOM=1 before writing the byte and then skip to
step 6)
B. If TFULL=1, then skip to step 5
4. Repeat step 3.
5. Wait for interrupt, skip to step 3.
6. Disable THALF or TNF interrupt and enable TMEND interrupt.
7. Wait for an interrupt, then read TUDR status bit to make sure packet was transmitted correctly.
14.4 HDLC REGISTER DESCRIPTION
HCR: HDLC CONTROL REGISTER (Address=B0 Hex)
(MSB)
(LSB)
RHR
TFS
THR
TABT
TEOM
TZSD
TCRCD
SYMBOLS
POSITION
NAME AND DESCRIPTION
HCR.7
Not Assigned. Should be set to zero.
RHR
HCR.6
Receive HDLC Reset. A 0 to 1 transition will reset the receive
HDLC controller. Must be cleared and set again for a
subsequent reset.
TFS
HCR.5
Transmit Flag/Idle Select.
0 = 7Eh.
1 = FFh.
THR
HCR.4
Transmit HDLC Reset. A 0 to 1 transition will reset the
transmit HDLC controller. Must be cleared and set again for a
subsequent reset.
TABT
HCR.3
Transmit Abort. A 0 to 1 transition will cause the FIFO
contents to be dumped and one FEh abort to be sent followed
by 7Eh or FFh flags/idle until a new packet is initiated by
writing new data into the FIFO. Must be cleared and set again
for a subsequent abort to be sent.
TEOM
HCR.2
Transmit End of Message. Should be set to a one just before
the last data byte of a HDLC packet is written into the transmit
FIFO at THFR. The HDLC controller will clear this bit when
the last byte has been transmitted.
TZSD
HCR.1
Transmit Zero Stuffer Defeat. Overrides internal enable.
0 = enable the zero stuffer (normal operation).
1 = disable the zero stuffer.
TCRCD
HCR.0
Transmit CRC Defeat.
0 = enable CRC generation (normal operation).
1 = disable CRC generation.
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參數(shù)描述
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