參數(shù)資料
型號: DS21FF42N
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA300
封裝: 27 X 27 MM, BGA-300
文件頁數(shù): 114/115頁
文件大小: 534K
代理商: DS21FF42N
DS21FF42/DS21FT42
98 of 115
RECEIVE SIDE INTERLEAVED BUS OPERATION FRAME MODE TIMING
Figure 24-7
TRANSMIT SIDE D4 TIMING Figure 24-8
FRAME#
12
3
4
5
6
7
8
9
10
11
12
1
23
45
1
2
3
4
TSYNC
TLCLK
TLINK
Notes:
1. TSYNC in the frame mode (TCR2.3 = 0) and double-wide frame sync is not enabled (TCR2.4 = 0)
2. TSYNC in the frame mode (TCR2.3 = 0) and double-wide frame sync is enabled (TCR2.4 = 1)
3. TSYNC in the multiframe mode (TCR2.3 = 1)
4. TLINK data (Fs - bits) is sampled during the F-bit position of even frames for insertion into the
outgoing T1 stream when enabled via TCR1.2
5. TLINK and TLCLK are not synchronous with TFSYNC
SS
g
RSER
LSB
SYSCLK
RSYNC
FRAMER 3, CHANNEL 32
MSB
LSB
FRAMER 0, CHANNEL 1
RSIG
D/B
C/D
B
A
C/A
B
FRAMER 3, CHANNEL 32
A
FRAMER 0, CHANNEL 1
MSB
LSB
FRAMER 0, CHANNEL 2
D/B
C/D
B
A
FRAMER 0, CHANNEL 2
Notes:
1. 4.096 MHz bus configuration.
2. 8.192 MHz bus configuration.
3. RSYNC is in the input mode (RCR2.3 = 1).
3
RSER
RSYNC
RSIG
FR1 CH1-32
FR0 CH1-32
FR1 CH1-32
RSER
RSIG
FR2 CH1-32 FR3 CH1-32 FR0 CH1-32
FR1 CH1-32
FR2 CH1-32
FR3 CH1-32
FR0 CH1-32
FR1 CH1-32
FR2 CH1-32
FR3 CH1-32
FR2 CH1-32 FR3 CH1-32 FR0 CH1-32
FR1 CH1-32
FR2 CH1-32
FR3 CH1-32
FR0 CH1-32
FR1 CH1-32
FR2 CH1-32
FR3 CH1-32
FR0 CH1-32
FR1 CH1-32
FR0 CH1-32
FR1 CH1-32
FR0 CH1-32
FR1 CH1-32
1
2
BIT DETAIL
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