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DS21FT42/DS21FF42
5 of 114
17.
ELASTIC STORES OPERATION..............................................................................................61
17.1
RECEIVE SIDE....................................................................................................................................................... 62
17.2
TRANSMIT SIDE ................................................................................................................................................... 62
17.3
MINIMUM DELAY SYNCHRONOUS RSYSCLK/TSYSCLK MODE ........................................................... 62
18.
HDLC CONTROLLER ................................................................................................................63
18.1
HDLC FOR DS0S ...................................................................................................................................................... 63
19.
FDL/FS EXTRACTION AND INSERTION ..............................................................................64
19.1
HDLC AND BOC CONTROLLER FOR THE FDL ........................................................................................... 64
19.1.1
General Overview.............................................................................................................................................. 64
19.1.2
Status Register for the HDLC .......................................................................................................................... 65
19.1.3
HDLC/BOC Register Description .................................................................................................................... 67
19.2
LEGACY FDL SUPPORT...................................................................................................................................... 75
19.2.1
Overview............................................................................................................................................................ 75
19.2.2
Receive Section ................................................................................................................................................. 75
19.2.3
Transmit Section............................................................................................................................................... 76
19.3
D4/SLC–96 OPERATION ...................................................................................................................................... 77
20.
PROGRAMMABLE IN-BAND CODE GENERATION AND DETECTION ........................77
21.
TRANSMIT TRANSPARENCY..................................................................................................80
22.
INTERLEAVED PCM BUS OPERATION................................................................................81
23.
JTAG-BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT .......................83
23.1
DESCRIPTION ............................................................................................................................................................ 83
23.2
TAP CONTROLLER STATE MACHINE...................................................................................................................... 84
23.3
INSTRUCTION REGISTER AND INSTRUCTIONS ......................................................................................................... 87
23.4
TEST REGISTERS....................................................................................................................................................... 89
24.
TIMING DIAGRAMS...................................................................................................................94
25.
OPERATING PARAMETERS ..................................................................................................102
26.
MCM PACKAGE DIMENSIONS .............................................................................................113