參數(shù)資料
型號: DS21FF42
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA300
封裝: 27 X 27 MM, BGA-300
文件頁數(shù): 59/115頁
文件大小: 534K
代理商: DS21FF42
DS21FF42/DS21FT42
48 of 115
SR2: STATUS REGISTER 2 (Address=21 Hex)
(MSB)
(LSB)
RMF
TMF
SEC
RFDL
TFDL
RMTCH
RAF
RSC
SYMBOL
POSITION
NAME AND DESCRIPTION
RMF
SR2.7
Receive Multiframe. Set on receive multiframe boundaries.
TMF
SR2.6
Transmit Multiframe. Set on transmit multiframe
boundaries.
SEC
SR2.5
One Second Timer. Set on increments of one second based
on RCLK; will be set in increments of 999 ms, 999 ms, and
1002 ms every 3 seconds.
RFDL
SR2.4
Receive FDL Buffer Full. Set when the receive FDL buffer
(RFDL) fills to capacity (8 bits).
TFDL
SR2.3
Transmit FDL Buffer Empty. Set when the transmit FDL
buffer (TFDL) empties.
RMTCH
SR2.2
Receive FDL Match Occurrence. Set when the RFDL
matches either RMTCH1 or RMTCH2.
RAF
SR2.1
Receive FDL Abort. Set when eight consecutive one’s are
received in the FDL.
RSC
SR2.0
Receive Signaling Change. Set when the DS21Q42 detects
a change of state in any of the robbed–bit signaling bits.
IMR1: INTERRUPT MASK REGISTER 1 (Address=7F Hex)
(MSB)
(LSB)
LUP
LDN
LOTC
SLIP
RBL
RYEL
RCL
RLOS
SYMBOL
POSITION
NAME AND DESCRIPTION
LUP
IMR1.7
Loop Up Code Detected.
0 = interrupt masked
1 = interrupt enabled
LDN
IMR1.6
Loop Down Code Detected.
0 = interrupt masked
1 = interrupt enabled
LOTC
IMR1.5
Loss of Transmit Clock.
0 = interrupt masked
1 = interrupt enabled
SLIP
IMR1.4
Elastic Store Slip Occurrence.
0 = interrupt masked
1 = interrupt enabled
RBL
IMR1.3
Receive Blue Alarm.
0 = interrupt masked
1 = interrupt enabled
RYE
IMR1.2
Receive Yellow Alarm.
0 = interrupt masked
1 = interrupt enabled
相關PDF資料
PDF描述
DS21FF42N DATACOM, FRAMER, PBGA300
DS21FT44N DATACOM, FRAMER, PBGA300
DS21FT44 DATACOM, FRAMER, PBGA300
DS21Q352 DATACOM, PCM TRANSCEIVER, PBGA256
DS21Q354 DATACOM, PCM TRANSCEIVER, PBGA256
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