參數(shù)資料
型號: DS2153Q-A7+T&R
廠商: Maxim Integrated Products
文件頁數(shù): 2/60頁
文件大?。?/td> 0K
描述: IC TXRX E1 1-CHIP 5V 44-PLCC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 500
功能: 單芯片收發(fā)器
接口: E1
電路數(shù): 1
電源電壓: 4.75 V ~ 5.25 V
電流 - 電源: 65mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC(16.59x16.59)
包裝: 帶卷 (TR)
DS2153Q
10 of 60
4 CONTROL AND TEST REGISTERS
The operation of the DS2153Q is configured via a set of seven registers. Typically, the control registers
are only accessed when the system is first powered up. Once the DS2153Q has been initialized, the
control registers only need to be accessed when there is a change in the system configuration. There are
two Receive Control Registers (RCR1 and RCR2), two Transmit Control Registers (TCR1 and TCR2),
and three Common Control Registers (CCR1, CCR2, and CCR3). Each of the seven registers is described
in this section. The LICR is described in Section 13.
The Test Registers at addresses 15 and 19 hex are used by the factory in testing the DS2153Q. On power-
up, the Test Registers should be set to 00 hex in order for the DS2153Q to operate properly.
RCR1: RECEIVE CONTROL REGISTER 1 (Address = 10B Hex)
(MSB)
(LSB)
RSMF
RSM
RSIO
FRC
SYNCE
RESYNC
SYMBOL
POSITION
NAME AND DESCRIPTION
RSMF
RCR1.7
RSYNC Multiframe Function. Only used if the RSYNC pin is
programmed in the multiframe mode (RCR1.6 = 1).
0 = RSYNC outputs CAS multiframe boundaries
1 = RSYNC outputs CRC4 multiframe boundaries
RSM
RCR1.6
RSYNC Mode Select.
0 = frame mode (see the timing in Section 14)
1 = multiframe mode (see the timing in Section 14)
RSIO
RCR1.5
RSYNC I/O Select.
0 = RSYNC is an output (depends on RCR1.6)
1 = RSYNC is an input (only valid if elastic store enabled) (Note:
this bit must be set to 0 when RCR2.1 = 0)
RCR1.4
Not Assigned. Should be set to 0 when written.
RCR1.3
Not Assigned. Should be set to 0 when written.
FRC
RCR1.2
Frame Resync Criteria.
0 = resync if FAS received in error 3 consecutive times
1 = resync if FAS or bit 2 of non-FAS is received in error 3
consecutive times
SYNCE
RCR1.1
Sync Enable.
0 = auto resync enabled
1 = auto resync disabled
RESYNC
RCR1.0
Resync. When toggled from low to high, a resync is initiated. Must
be cleared and set again for a subsequent resync.
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