參數資料
型號： DS2153Q-A7+T&R
廠商： Maxim Integrated Products
文件頁數： 10/60頁
文件大小： 0K
描述： IC TXRX E1 1-CHIP 5V 44-PLCC
產品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 500
功能： 單芯片收發(fā)器
接口： E1
電路數： 1
電源電壓： 4.75 V ~ 5.25 V
電流 - 電源： 65mA
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 44-LCC（J 形引線）
供應商設備封裝： 44-PLCC（16.59x16.59）
包裝： 帶卷 (TR)
DS2153Q
18 of 60
5 STATUS AND INFORMATION REGISTERS
There is a set of four registers that contain information on the current real-time status of the DS2153Q:
Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Register (RIR), and Synchronizer
Status Register (SSR). When a particular event has occurred (or is occurring), the appropriate bit in one
of these four registers will be set to a 1. All of the bits in these registers operate in a latched fashion
(except for the SSR). This means that if an event occurs and a bit is set to a 1 in any of the registers, it
will remain set until the user reads that bit. The bit will be cleared when it is read and it will not be set
again until the event has occurred again or if the alarm is still present.
The user will always precede a read of the SR1, SR2, and RIR registers with a write. The byte written to
the register will inform the DS2153Q which bits the user wishes to read and have cleared. The user will
write a byte to one of these three registers, with a 1 in the bit positions he or she wishes to read and a 0 in
the bit positions he or she does not wish to obtain the latest information on. When a 1 is written to a bit
location, the read register will be updated with current value and it will be cleared. When a 0 is written to
a bit position, the read register will not be updated and the previous value will be held. A write to the
status and information registers will be immediately followed by a read of the same register. The read
result should be logically ANDed with the mask byte that was just written and this value should be
written back into the same register to insure that bit does indeed clear. This second write step is necessary
because the alarms and events in the status registers occur asynchronously in respect to their access via
the parallel port. This write-read-write scheme allows an external microcontroller or microprocessor to
individually poll certain bits without disturbing the other bits in the register. This operation is key in
controlling the DS2153Q with higher-order software languages.
The SSR register operates differently than the other three. It is a read-only register and it reports the status
of the synchronizer in real time. This register is not latched and it is not necessary to precede a read of
this register with a write.
The SR1 and SR2 registers have the unique ability to initiate a hardware interrupt via the INT1 and INT2
pins, respectively. Each of the alarms and events in the SR1 and SR2 can be either masked or unmasked
from the interrupt pins via the Interrupt Mask Register 1 (IMR1) and Interrupt Mask Register 2 (IMR2),
respectively.
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相關代理商/技術參數
參數描述
DS2153QN 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM Transceiver
DS2153QN-A5 功能描述:IC TXRX E1 1-CHIP 5V IND 44-PLCC RoHS:否 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS 產品變化通告:Product Discontinuation 06/Feb/2012 標準包裝:750 系列:*
DS2153QN-A7 功能描述:網絡控制器與處理器 IC RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2153QN-A7/T&R 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述:
DS2153QN-A7/T&R+ 制造商:Maxim Integrated Products 功能描述:FRAMER E1/ISDN-PRI/PCM-30 5V 44PLCC - Tape and Reel
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