參數(shù)資料
型號(hào)： DS2149Q+T&R
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 32/32頁(yè)
文件大小： 0K
描述： IC LIU T1/J1 5V 28-PLCC
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 500
類型： 線路接口裝置（LIU）
規(guī)程： T1/J1
電源電壓： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
封裝/外殼： 28-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 28-PLCC（11.51x11.51）
包裝： 帶卷 (TR)
DS2149
9 of 32
3. INITIALIZATION AND RESET
During power-up, all control registers are cleared, disabling the transmitter outputs. The device requires a
master clock supplied to the MCLK input pin to operate the PLL. This master clock must be independent,
free-running, and jitter free.
A reset initializes the status and state machines for the RCL, AIS, NLOOP, and QRSS blocks. Under
software control, setting the RESET bit (CR2.7) clears all registers. Allow up to 100ms for the receiver to
recover from initialization.
4. REGISTER DEFINITIONS
The DS2149 contains eight registers for configuring the device and reading status. These are accessible
using the serial port. Table 4-A lists the register names and addresses.
Reading or writing to the internal registers requires writing one address/command byte prior to
transferring register data. The first bit written (LSb) of the address/command byte specifies whether the
access is a read (1) or a write (0). The next 6 bits identify the register address.
The last bit (MSb) of the address/command byte is the burst mode bit. When the burst bit is enabled (set
to 1) and a READ operation is performed, addresses 10h through 17h are read sequentially, starting at
address 10h. And when the burst bit is enabled and a WRITE operation is performed, addresses 10h
through 17h are written sequentially, starting at address 10h. Burst operation is stopped once address 17h
is read. All data transfers are initiated by driving the
CS input low. All data transfers are terminated if the
CS input transitions high. Port control logic is disabled and SDO is tri-stated when CS is high.
Table 4-A. Register Map
REGISTER
SYMBOL
ADDRESS
Control Register 1
CR1
B010000
Control Register 2
CR2
B010001
Control Register 3
CR3
B010010
Interrupt Mask Register
IMR
B010011
Transition Status Register
TSR
B010100
Status Register
SR
B010101
Information Register
IR
B010110
Control Register 4
CR4
B010111
Table 4-B. Register Bit Positions
SYMBOL 7 (MSb)
6
5
4
3
2
1
0 (LSb)
CR1
JASEL1
JASEL0
ENCENB
UNIENB
L3
L2
L1
L0
CR2
RESET
PAT1
PAT0
TAIS
ENLOOP
ALB
LLB
RLB
CR3
JA6HZ
TPD
—
EQZMON20 EQZMON26
JA128
LIRST
TAOZ
IMR
Z16D
JALT
DFMO
B8ZSD
QRSS
AIS
NLOOP
RCL
TSR
Z16D
JALT
DFMO
B8ZSD
QRSS
AIS
NLOOP
RCL
SR
—
DFMO
—
QRSS
AIS
NLOOP
RCL
IR
RL3
RL2
RL1
RL0
LUP
LDN
TSCD
LOTC
CR4
—
RCL2048
XFMR2
XFMR1
Note: Set unused bits to 0 for normal operation.
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