參數(shù)資料
型號: DS1877T+T&R
廠商: Maxim Integrated Products
文件頁數(shù): 42/65頁
文件大?。?/td> 0K
描述: IC CTLR/MON SFP 1-2CH 28TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: SFP+ 控制器
輸入類型: 邏輯
輸出類型: 邏輯
接口: I²C
電流 - 電源: 2.5mA
安裝類型: 表面貼裝
封裝/外殼: 28-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 28-TQFN-EP(5x5)
包裝: 帶卷 (TR)
其它名稱: 90-1877T+TRL
47
Maxim Integrated
SFP Controller for Dual Rx Interface
DS1877
Table 02h, Register 8Ah: CNFGC
Table 02h, Register 8Bh: DEVICE ADDRESS
FACTORY DEFAULT
00h
READ ACCESS
PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS
PW2 or (PW1 and RWTBL2)
A2h AND B2h MEMORY
Common A2h and B2h memory locations
MEMORY TYPE
Nonvolatile (SEE)
8Ah
RESERVED
TXD_RST
EN DAC2
LOSC2
INVLOS2
RESERVED
TXD_RST
EN DAC1
LOSC1
INVLOS1
BIT 7
BIT 0
BITS 7, 3
RESERVED
BIT 6
TXD_RST EN DAC2:
0 = TXDC2 has no effect on DAC2.
1 = DAC2 is reset by TXDC2.
BIT 5
LOSC2: See Figure 11.
0 = LOS2 LO QT drives LOSOUT logic.
1 = LOS2 input pin drives LOSOUT logic.
BIT 4
INVLOS2: See Figure 11.
0 = (default) LOS2 input is not inverted.
1 = LOS2 input is inverted.
BIT 2
TXD_RST EN DAC1: See Figure 11.
0 = TXDC1 has no effect on DAC1.
1 = DAC1 is reset by TXDC1.
BIT 1
LOSC1: See Figure 11.
0 = LOS1 LO QT drives LOSOUT logic.
1 = LOS1 input pin drives LOSOUT logic.
BIT 0
INVLOS1: See Figure 11.
0 = (default) LOS1 input is not inverted.
1 = LOS1 input is inverted.
FACTORY DEFAULT
00h
READ ACCESS
PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS
PW2 or (PW1 and RWTBL2)
A2h AND B2h MEMORY
Common A2h and B2h memory locations
MEMORY TYPE
Nonvolatile (SEE)
8Bh
RESERVED
23
22
21
RESERVED
BIT 7
BIT 0
This value becomes the I2C slave address for the main memory when the ASEL bit (Table 02h, Register 88h) is
set. If A0h/B0h is programmed to this register, the auxiliary memory is disabled. For example, writing xxxx_010x
makes the main device addresses A4h and B4h.
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