參數(shù)資料
型號： DS1876T+T&R
廠商： Maxim Integrated Products
文件頁數(shù)： 28/69頁
文件大小： 0K
描述： IC CTRLR SFP DUAL LDD 28TQFN
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 2,500
類型： SFP 激光控制器
輸入類型： 邏輯
輸出類型： 邏輯
接口： I²C
電流 - 電源： 10mA
安裝類型： 表面貼裝
封裝/外殼： 28-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 28-TQFN-EP（5x5）
包裝： 帶卷 (TR)
34
Maxim Integrated
SFP Controller with Dual LDD Interface
DS1876
Lower Memory, Register 6Eh: STATUS
POWER-ON VALUE
X0XX 0XXXb
READ ACCESS
All
WRITE ACCESS
See below
A2h AND B2h MEMORY
Mixture of common memory locations and different memory locations (see below)
MEMORY TYPE
Volatile
Write Access
N/A
All
N/A
All
N/A
6Eh
<D>TXDS
<D>TXDC
<C>IN1S
<C>RSELS
<C>RSELC
<D>TXFS
<D>RAM
<C>RDYB
BIT 7
BIT 0
BIT 7
TXDS1 [A2h]: TXD1 status bit. Reflects the logic state of the TXD1 pin (read-only).
0 = TXD1 pin is logic-low.
1 = TXD1 pin is logic-high.
TXDS2 [B2h]: TXD2 status bit. Reflects the logic state of the TXD2 pin (read-only).
0 = TXD2 pin is logic-low.
1 = TXD2 pin is logic-high.
BIT 6
TXDC1 [A2h]: TXD1 software control bit. This bit allows for software control that is identical to the
TXD1 pin. See the DACs as a Function of Transmit Disable (TXD1, TXD2) section for further infor-
mation. Its value is wire-ORed with the logic value of the TXD1 pin (writable by all users).
0 = (default)
1 = Forces the device into a TXD1 state regardless of the value of the TXD1 pin.
TXDC2 [B2h]: TXD2 software control bit. This bit allows for software control that is identical to the
TXD2 pin. See the DACs as a Function of Transmit Disable (TXD1, TXD2) section for further infor-
mation. Its value is wire-ORed with the logic value of the TXD2 pin (writable by all users).
0 = (default)
1 = Forces the device into a TXD2 state regardless of the value of the TXD2 pin.
BIT 5
IN1S [A2h or B2h]: IN1 status bit. Reflects the logic state of the IN1 pin (read-only).
0 = IN1 pin is logic-low.
1 = IN1 pin is logic-high.
BIT 4
RSELS [A2h or B2h]: RSEL status bit. Reflects the logic state of the RSEL pin (read-only).
0 = RSEL pin is logic-low.
1 = RSEL pin is logic-high.
BIT 3
RSELC [A2h or B2h]: RSEL software control bit. This bit allows for software control that is iden-
tical to the RSEL pin. Its value is wire-ORed with the logic value of the RSEL pin to create the
RSELOUT pin’s logic value (writable by all users).
0 = (default)
1 = Forces the device into a RSEL state regardless of the value of the RSEL pin.
BIT 2
TXFS1 [A2h]: Reflects state of the TXF1 pin (read-only).
0 = TXF1 pin is low.
1 = TXF1 pin is high.
TXFS2 [B2h]: Reflects the state of the TXF2 pin (read-only).
0 = TXF2 pin is low.
1 = TXF2 pin is high.
BIT 1
RAM1 [A2h]: Volatile memory location.
RAM2 [B2h]: Volatile memory location.
BIT 0
RDYB [A2h or B2h]: Ready bar.
0 = VCC is above POA.
1 = VCC is below POA and/or too low to communicate over the I2C bus.
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