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參數(shù)資料
| 型號： | DS1859E-050/T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 4/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RES TEMP 50/50K 3MON 16-TSSOP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1,000 |
| 接片： | 256 |
| 電阻（歐姆）： | 50k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標準值 50 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設備位址） |
| 電源電壓： | 2.85 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 95°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
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DS1859
Dual, Temperature-Controlled Resistors with
Internally Calibrated Monitors
12
____________________________________________________________________
above is accessible only through the Main Device
address. This memory is organized as three tables. The
desired table can be selected by the contents of mem-
ory location 7Fh, Main Device. The Auxiliary Device
address has no access to the tables, but the Auxiliary
Device address can be mapped into the Main Device’s
memory space as a fourth table. Device addresses are
programmable with two control bits in EEPROM.
ADEN configures memory access to respond to differ-
ent device addresses (see Tables 4 and 5).
The default device address for EEPROM-generated
addresses is A2h.
If the ADEN bit is 1, additional 128 bytes of EEPROM
are accessible through the Main Device, selected as
Table 00 (see Figure 3). In this configuration, the
Auxiliary Device is not accessible. APEN controls the
protection of Table 00 regardless of ADEN’s setting.
ADFIX (address fixed) determines whether the Main
Device address is determined by an EEPROM byte
(Table 01, byte 8Ch, when ADFIX = 1). There can be
up to 128 devices sharing a common 2-wire bus, with
each device having its own unique device address.
WPEN
MPEN
PROTECT MAIN
0X
No
X0
No
11
Yes
Table 6. Main Device
APEN
WPEN
PROTECT AUXILIARY
0
XNo
1
X
Yes
Table 7. Auxiliary Device
MAIN
DEVICE
MON LOOK-UP
TABLE CONTROL
R0 LOOK-UP
TABLE
AUXILIARY
DEVICE
80h
DEC
0
95
96
127
128
143
199
255
EN
5Fh
60h
EN
SEL
EN
SEL
FFh
7Fh
80h
C7h
F0h
FFh
RESERVED
8Fh
TABLE SELECT
TABLE 00
MAIN DEVICE ENABLE
DECODER
0
F0h
FFh
RESERVED
R1 LOOK-UP
TABLE
EN
SEL
80h
C7h
TABLE 03
TABLE 02
TABLE 01
MEMORY PARTITION WITH ADEN BIT = 1
Figure 3. Memory Organization, ADEN = 1
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