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參數(shù)資料
| 型號： | DS1859E-050/T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 3/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RES TEMP 50/50K 3MON 16-TSSOP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1,000 |
| 接片： | 256 |
| 電阻（歐姆）： | 50k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標準值 50 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設備位址） |
| 電源電壓： | 2.85 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 95°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
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DS1859
Dual, Temperature-Controlled Resistors with
Internally Calibrated Monitors
____________________________________________________________________
11
Variable Resistors
The value of each variable resistor is determined by
a temperature-addressed look-up table, which can
assign a unique value (00h to FFh) to each resistor for
every 2°C increment over the -40°C to +102°C range
(see Table 3). See the Temperature Conversion section
for more information.
The variable resistors can also be used in manual
mode. If the TEN bit equals 0, the resistors are in manu-
al mode and the temperature indexing is disabled. The
user sets the resistors in manual mode by writing to
addresses 82h and 83h in Table 01 to control resistors
0 and 1, respectively.
Memory Description
Main and auxiliary memories can be accessed by two
separate device addresses. The Main Device address
is A2h (or value in Table 01 byte 8Ch, when ADFIX = 1)
and the Auxiliary Device address is A0h. A user option
is provided to respond to one or two device addresses.
This feature can be used to save component count in
SFF applications (Main Device address can be used)
or other applications where both GBIC (Auxiliary
Device address can be used) and monitoring functions
are implemented and two device addresses are need-
ed. The memory blocks are enabled with the corre-
sponding device address. Memory space from 80h and
ADEN
(ADDRESS
ENABLE)
NO. OF SEPARATE
DEVICE
ADDRESSES
ADDITIONAL
INFORMATION
02
See Figure 2
1
1 (Main Device only)
See Figure 3
Table 4. ADEN Address Configuration
ADEN
ADFIX
AUXILIARY
ADDRESS
MAIN ADDRESS
00
A0h
A2h
01
A0h
EEPROM
(Table 01, 8Ch)
10
N/A
A2h
11
N/A
EEPROM
(Table 01, 8Ch)
Table 5. ADEN and ADFIX Bits
MAIN
DEVICE
MON LOOK-UP
TABLE CONTROL
R0 LOOK-UP
TABLE
AUXILIARY
DEVICE
0
DEC
0
95
96
127
128
143
199
MEMORY PARTITION WITH ADEN BIT = 0
EN
5Fh
60h
EN
SEL
EN
SEL
7Fh
80h
C7h
F0h
FFh
RESERVED
8Fh
TABLE SELECT
MAIN DEVICE ENABLE
AUXILIARY DEVICE ENABLE
DECODER
0
F0h
FFh
RESERVED
R1 LOOK-UP
TABLE
EN
SEL
80h
C7h
TABLE 03
TABLE 02
TABLE 01
Figure 2. Memory Organization, ADEN = 0
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