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參數(shù)資料
| 型號(hào)： | DS18030-100+ |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 10/11頁(yè) |
| 文件大小： | 0K |
| 描述： | IC POT DUAL ADDRESS 100K 16-DIP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 25 |
| 接片： | 256 |
| 電阻（歐姆）： | 100k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 750 ppm/°C |
| 存儲(chǔ)器類(lèi)型： | 易失 |
| 接口： | I²C（芯片選擇） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 通孔 |
| 封裝/外殼： | 16-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 16-PDIP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁(yè)面： | 1431 (CN2011-ZH PDF) |
DS1803
8 of 11
5. After this period, the first clock pulse is generated.
6. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the
VIHMIN of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
7. The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the
SCL signal.
8. A fast mode device can be used in a standard mode system, but the requirement tSU:DAT > 250 ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line tRMAX+ tSU:DAT = 1000 + 250=1250 ns before the SCL line is released.
9. CB - total capacitance of one bus line in picofarads, timing referenced to (0.9)(VCC) and (0.1)(VCC).
10. Typical values are for tA = 25°C and nominal supply voltage.
11. -3 dB cutoff frequency characteristics for the DS1803 depend on potentiometer total resistance:
DS1803-010; 1 MHz, DS1803-50; 200 kHz, DS1803-100; 100 kHz.
12. Address Inputs, A0, A1, and A2, should be tied to either VCC or GND depending on the desired
address selections.
13. Absolute linearity is used to determine wiper voltage versus expected voltage as determined by wiper
position. Device test limits are
±1.6 LSB.
14. Relative linearity is used to determine the change in voltage between successive tap positions. Device
test limits
±0.5 LSB.
15. Fast mode.
16. Standard mode.
17. Valid at 25
°C only.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS18030-100+ | 功能描述:數(shù)字電位計(jì) IC Addressable Dual RoHS:否 制造商:Maxim Integrated 電阻:200 Ohms 溫度系數(shù):35 PPM / C 容差:25 % POT 數(shù)量:Dual 每 POT 分接頭:256 弧刷存儲(chǔ)器:Volatile 緩沖刷: 數(shù)字接口:Serial (3-Wire, SPI) 描述/功能:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 工作電源電壓:1.7 V to 5.5 V 電源電流:27 uA 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFN-16 封裝:Reel |
| DS1803-050 | 制造商:Maxim Integrated Products 功能描述:- Rail/Tube |
| DS1803-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:IC-10K DUAL POT |
| DS1803-100 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Addressable Dual Digital Potentiometer |
| DS1803-50 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:IC-50K DUAL POT |
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