Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in " />
參數(shù)資料
型號(hào): DS1486P-120+
廠商: Maxim Integrated Products
文件頁數(shù): 6/14頁
文件大?。?/td> 0K
描述: IC TIMEKEEPER RAM 1MB 34-PCM
標(biāo)準(zhǔn)包裝: 40
類型: 時(shí)鐘/日歷
特點(diǎn): 警報(bào)器,閏年,NVSRAM,方波輸出,監(jiān)視計(jì)時(shí)器
存儲(chǔ)容量: 128KB
時(shí)間格式: HH:MM:SS:hh(12/24 小時(shí))
數(shù)據(jù)格式: YY-MM-DD-dd
接口: 并聯(lián)
電源電壓: 4.5 V ~ 5.5 V
電壓 - 電源,電池: 3.3V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 34-PowerCap? 模塊
供應(yīng)商設(shè)備封裝: 34-PowerCap 模塊
包裝: 管件
DS1486/DS1486P
14 of 14
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Ma xi m Integr at ed Pr oducts, 120 San Gabr i el Dr ive, Sunnyval e, CA 94086 40 8- 737- 7600
2005 Maxim Integrated Products
Printed USA
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.
NOTES:
1)
WE is high for a read cycle.
2)
OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state.
3) tWP is specified as the logical AND of the CE and WE. tWP is measured from the latter of CE or WE
going low to the earlier of
CE or WE going high.
4) tDS or tDH are measured from the earlier of CE or WE going high.
5) tDH is measured from WE going high. If CE is used to terminate the write cycle, then tDH = 20ns.
6) If the
CE low transition occurs simultaneously with or later than the WE low transition in write cycle
1, the output buffers remain in a high-impedance state during this period.
7) If the
CE high transition occurs prior to or simultaneously with the WE high transition, the output
buffers remain in a high impedance state during this period.
8) If
WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition,
the output buffers remain in a high-impedance state during this period.
9) Each DS1486 is marked with a four-digit date code AABB. AA designates the year of manufacture.
BB designates the week of manufacture. The expected tDR is defined for DIP Modules as starting at
the date of manufacture.
10) All voltages are referenced to ground.
11) Applies to both interrupt pins when the alarms are set to pulse.
12) Interrupt output occurs within 100ns on the alarm condition existing.
13) Both
INTA and INTB (INTB) are open-drain outputs.
14) Real-Time Clock Modules (DIP) can be successfully processed through conventional wave-soldering
techniques as long as temperature exposure to the lithium energy source contained within does not
exceed +85
°C. Post-solder cleaning with water washing techniques is acceptable, provided that
ultrasonic vibration is not used. See the PowerCap package drawing for details regarding the
PowerCap package.
AC TEST CONDITIONS
Output Load: 50pF + 1TTL Gate
Input Pulse Levels: 0 to 3.0V
Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5ns
PACKAGE INFORMATION
For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.
28-pin 740 EDIP Module Document number: 56-G0002-001
32-pin PowerCap Module Document number: 56-G0003-001
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