參數(shù)資料
型號: DS1124U-25+T
廠商: Maxim Integrated Products
文件頁數(shù): 8/10頁
文件大小: 0K
描述: IC DELAY LINE 256TAP 10-USOP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 3,000
標片/步級數(shù): 256
功能: 可編程
延遲到第一抽頭: 20ns
接頭增量: 0.25ns
可用的總延遲: 83.75ns
獨立延遲數(shù): 1
電源電壓: 4.75 V ~ 5.25 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應商設備封裝: 10-µMAX
包裝: 帶卷 (TR)
Figure 4C shows how to cascade multiple DS1124s onto
the same 3-wire bus. One important detail of writing
software for cascaded 3-wire devices is that all the
devices on the bus must be written to or read from
during each read or write cycle. Attempting to write to
only the first device (U1) would cause the data stored in
U1 to be shifted to U2, U2’s data would be shifted to U3,
etc. As shown, the microprocessor would have to shift
24 bits during each read or write cycle to avoid inadver-
tently changing the settings in any of the 3-wire devices.
Also note that the feedback resistor or a separate input
(not shown) can still be used to read the 3-wire device
settings when multiple devices are cascaded.
Integral Nonlinearity
Integral nonlinearity (INL) is defined as the deviation
from a straight line response drawn between the mea-
sured step zero delay (tD0) and the measured step 255
delay (tD255) with respect to the step 0 delay. Figure 5
shows INL’s effect on delay performance graphically.
Application Information
Power-Supply Decoupling
To achieve the best results when using the DS1124,
decouple the power supply with a 0.01F and a 0.1F
capacitor. Use high-quality, ceramic, surface mount
capacitors, and mount the capacitors as close as possi-
ble to the VCC and GND pins of the DS1124 to minimize
lead inductance. The DS1124 may not perform as speci-
fied if good decoupling practices are not followed.
DS1124
5.0V 8-Bit Programmable
Timing Element
_______________________________________________________________________________________
7
tCW
tCQV
tCQX
tES
tDSC
tEQV
tDHC
tCW
tEW
tEH
tEQZ
tEDV
tEDX
CLOCK
(CLK)
DELAY
TIME
SERIAL
INPUT
(D)
SERIAL
OUTPUT
(Q)
OLD BIT 7
OLD BIT 6
OLD BIT 0
ENABLE
(E)
NEW VALUE
NEW BIT 7
NEW BIT 0
PREVIOUS VALUE
NEW BIT 6
Figure 3. Serial Interface Timing Diagram
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