VCC (Pin 1): Positive Supply Voltage. Bypass to GND (Pi" />
參數(shù)資料
型號： DC586A
廠商： Linear Technology
文件頁數(shù)： 40/40頁
文件大?。?/td> 0K
描述： BOARD DELTA SIGMA ADC LTC2431
軟件下載： QuikEval System
設(shè)計資源： DC586A Design File
DC586A Schematic
標(biāo)準(zhǔn)包裝： 1
系列： QuikEval™
ADC 的數(shù)量： 2
位數(shù)： 20
采樣率（每秒）： 7.5
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
工作溫度： 0°C ~ 70°C
已用 IC / 零件： LTC2431
已供物品： 板
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LTC2431IMS#TRPBF-ND - IC ADC 20BIT DIFFINPUT/REF10MSOP
LTC2431CMS#PBF-ND - IC ADC 20BIT DIFFINPUT/REF10MSOP
LTC2431CMS-ND - IC ADC 20BIT DIFFINPUT/REF10MSOP
LTC2431IMSTR-ND - IC ADC 20BIT DIFFINPUT/REF10MSOP
LTC2431IMS-ND - IC ADC 20BIT DIFFINPUT/REF10MSOP
LTC2431CMSTR-ND - IC ADC 20BIT DIFFINPUT/REF10MSOP
LTC2430/LTC2431
9
24301f
VCC (Pin 1): Positive Supply Voltage. Bypass to GND
(Pin 6) with a 10
F tantalum capacitor in parallel with
0.1
F ceramic capacitor as close to the part as possible.
REF+ (Pin 2), REF– (Pin 3): Differential Reference Input.
The voltage on these pins can have any value between GND
and VCC as long as the reference positive input, REF+, is
maintained more positive than the reference negative
input, REF –, by at least 0.1V.
IN+ (Pin 4), IN– (Pin 5): Differential Analog Input. The
voltage on these pins can have any value between
GND – 0.3V and VCC + 0.3V. Within these limits, the
converter bipolar input range (VIN = IN+ – IN–) extends
from – 0.5 (VREF) to 0.5 (VREF). Outside this input
range, the converter produces unique overrange and
underrange output codes.
GND (Pin 6): Ground. Connect this pin to a ground plane
through a low impedance connection.
CS (Pin 7): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion, the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.
UU
U
PI FU CTIO S
GND (Pins 1, 7, 8, 9, 10, 15, 16): Ground. Multiple ground
pins internally connected for optimum ground current flow
and VCC decoupling. Connect each one of these pins to a
ground plane through a low impedance connection. All seven
pins must be connected to ground for proper operation.
VCC (Pin 2): Positive Supply Voltage. Bypass to GND with
a 10
F tantalum capacitor in parallel with 0.1F ceramic
capacitor as close to the part as possible.
REF+ (Pin 3), REF– (Pin 4): Differential Reference Input.
The voltage on these pins can have any value between GND
and VCC as long as the reference positive input, REF+, is
maintained more positive than the reference negative
input, REF –, by at least 0.1V.
IN+ (Pin 5), IN– (Pin 6): Differential Analog Input. The
voltage on these pins can have any value between
GND – 0.3V and VCC + 0.3V. Within these limits the
converter bipolar input range (VIN = IN+ – IN–) extends
from – 0.5 (VREF) to 0.5 (VREF). Outside this input range
the converter produces unique overrange and underrange
output codes.
CS (Pin 11): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.
SDO (Pin 12): Three-State Digital Output. During the Data
Output period, this pin is used as serial data output. When
the chip select CS is HIGH (CS = VCC) the SDO pin is in a
high impedance state. During the Conversion and Sleep
periods, this pin is used as the conversion status output.
The conversion status can be observed by pulling CS LOW.
SCK (Pin 13): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as digital output
for the internal serial interface clock during the Data
Output period. In External Serial Clock Operation mode,
SCK is used as digital input for the external serial interface
clock during the Data Output period. A weak internal pull-
up is automatically activated in Internal Serial Clock Op-
eration mode. The Serial Clock Operation mode is deter-
mined by the logic level applied to the SCK pin at power up
or during the most recent falling edge of CS.
FO (Pin 14): Frequency Control Pin. Digital input that
controls the ADC’s notch frequencies and conversion
time. When the FO pin is connected to VCC (FO = VCC), the
converter uses its internal oscillator and the digital filter
first null is located at 50Hz. When the FO pin is connected
to GND (FO = OV), the converter uses its internal oscillator
and the digital filter first null is located at 60Hz. When FO
is driven by an external clock signal with a frequency fEOSC,
the converter uses this signal as its system clock and the
digital filter first null is located at a frequency fEOSC/2560.
(LTC2430)
(LTC2431)
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