參數(shù)資料
型號(hào)： DC586A
廠(chǎng)商： Linear Technology
文件頁(yè)數(shù)： 11/40頁(yè)
文件大小： 0K
描述： BOARD DELTA SIGMA ADC LTC2431
軟件下載： QuikEval System
設(shè)計(jì)資源： DC586A Design File
DC586A Schematic
標(biāo)準(zhǔn)包裝： 1
系列： QuikEval™
ADC 的數(shù)量： 2
位數(shù)： 20
采樣率（每秒）： 7.5
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
工作溫度： 0°C ~ 70°C
已用 IC / 零件： LTC2431
已供物品： 板
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LTC2430/LTC2431
19
24301f
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the sleep state and enter the data output
state if CS remains LOW. In order to allow the device to
return to the low power sleep state, CS must be pulled
HIGH before the first rising edge of SCK. In the internal
SCK timing mode, SCK goes HIGH and the device begins
outputting data at time tEOCtest after the falling edge of CS
(if EOC = 0) or tEOCtest after EOC goes LOW (if CS is LOW
during the falling edge of EOC). The value of tEOCtest is 23s
if the device is using its internal oscillator (FO = logic LOW
or HIGH). If FO is driven by an external oscillator of
frequency fEOSC, then tEOCtest is 3.6/fEOSC. If CS is pulled
HIGH before time tEOCtest, the device returns to the sleep
state. The conversion result is held in the internal static
shift register.
If CS remains LOW longer than tEOCtest, the first rising
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle begins on
this first rising edge of SCK and concludes after the 24th
rising edge. Data is shifted out the SDO pin on each falling
edge of SCK. The internally generated serial clock is output
to the SCK pin. This signal may be used to shift the
conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of the
conversion result on the 24th rising edge of SCK. After the
24th rising edge, SDO goes HIGH (EOC = 1), SCK stays
HIGH and a new conversion starts.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 24th rising edge of
SCK, see Figure 9. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
new conversion. This is useful for systems not requiring
all 24 bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion. If CS is
pulled HIGH while the converter is driving SCK LOW, the
Figure 9. Internal Serial Clock, Reduced Data Output Length
APPLICATIO S I FOR ATIO
WU
UU
SDO
SCK
(INTERNAL)
CS
>tEOCtest
MSB
SIG
BIT 8
TEST EOC
BIT 19
BIT 18
BIT 20
BIT 21
BIT 22
EOC
BIT 23
EOC
BIT 0
SLEEP
TEST EOC
(OPTIONAL)
SLEEP
DATA OUTPUT
Hi-Z
DATA
OUTPUT
CONVERSION
SLEEP
2431 F09
<tEOCtest
VCC
10k
TEST EOC
VCC
FO
REF+
REF–
SCK
IN+
IN–
SDO
GND
CS
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
3-WIRE
SPI INTERFACE
1
F
2.7V TO 5.5V
LTC2430/
LTC2431
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
VCC
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