參數(shù)資料
型號(hào)： DC1571A-C
廠商： Linear Technology
文件頁(yè)數(shù)： 7/24頁(yè)
文件大?。?/td> 0K
描述： BOARD SAR ADC LTC2381-16
軟件下載： QuikEval II System
設(shè)計(jì)資源： DC1571A Design Files
DC1571A Schematic
標(biāo)準(zhǔn)包裝： 1
系列： QuikEval™
ADC 的數(shù)量： 1
位數(shù)： 16
采樣率（每秒）： 250k
數(shù)據(jù)接口： 串行，SPI?
輸入范圍： ±2.5 V
在以下條件下的電源（標(biāo)準(zhǔn)）： 3.25mW @ 250kSPS
工作溫度： 0°C ~ 70°C
已用 IC / 零件： LTC2381-16
已供物品： 板
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更多...
LTC2381-16
15
238116f
Auto Power-Down
The LTC2381-16 automatically powers down after a
conversion has been completed as long as CNV remains
high. During power-down, the data from the last conversion
can be clocked out. To minimize power dissipation during
power-down, disable SDO and turn off SCK. To power up
the part, bring CNV low at least 200ns (tCONVL) before the
initiation of the next conversion. The auto power-down
feature will reduce the power dissipation of the LTC2381-
16 as the sampling frequency is reduced. Since the time
required to power up the part does not change at lower
sample rates, the LTC2381-16 can remain powered-down
for a larger fraction of the conversion cycle (tCYC), thereby
reducing the average power dissipation which scales
linearly with sampling rate as shown in Figure 11.
DIGITAL INTERFACE
The LTC2381-16 has a serial digital interface. The flexible
OVDD supply allows the LTC2381-16 to communicate with
any digital logic operating between 1.8V and 5V, including
2.5V and 3.3V systems.
The serial output data is clocked out on the SDO pin
when an external clock is applied to the SCK pin if SDO
is enabled. Clocking out the data after the conversion will
yield the best performance. With a shift clock frequency
of at least 15MHz, a 250ksps throughput is still achieved.
The serial output data changes state on the rising edge
of SCK and can be captured on the falling edge or next
rising edge of SCK. D15 remains valid till the first rising
edge of SCK.
The serial interface on the LTC2381-16 is simple and
straightforward to use. The following sections describe the
operation of the LTC2381-16. Several modes are provided
depending on whether a single or multiple ADCs share the
SPI bus or are daisy-chained.
APPLICATIONS INFORMATION
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