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參數(shù)資料
| 型號： | DC1571A-C |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 10/24頁 |
| 文件大小： | 0K |
| 描述： | BOARD SAR ADC LTC2381-16 |
| 軟件下載： | QuikEval II System |
| 設(shè)計資源： | DC1571A Design Files DC1571A Schematic |
| 標準包裝： | 1 |
| 系列： | QuikEval™ |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 250k |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 輸入范圍： | ±2.5 V |
| 在以下條件下的電源（標準）： | 3.25mW @ 250kSPS |
| 工作溫度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2381-16 |
| 已供物品： | 板 |
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LTC2381-16
18
238116f
TIMING DIAGRAM
OVDD
238116 F12
CONVERT
IRQ
DATA IN
DIGITAL HOST
CLK
CNV
LTC2381-16
BUSY
SDO
B
SCK
RDL/SDI
CNV
LTC2381-16
SDO
A
SCK
RDL/SDI
CHAIN
OVDD
CHAIN
When CHAIN = OVDD, the LTC2381-16 operates in Chain
Mode. In Chain Mode, SDO is always enabled and RDL/SDI
serves as the serial data input pin (SDI) where daisychain
data output from another ADC can be input.
This is useful for applications where hardware constraints
may limit the number of lines needed to interface to a large
number of converters. Figure 14 shows an example with
two daisy chained devices. The MSB of converter A will
appear at SDO of converter B after 16 SCK cycles. The
MSB of converter A is clocked in at the SDI/RDL pin of
converter B on the rising edge of the first SCK.
Figure 14. Chain Mode Timing Diagram
238116 F14
D0A
D1A
D14A
D15A
D13B
D14B
D15B
SDOB
SDOA = RDL/SDIB
RDL/SDIA = 0
D0B
D1B
D13A
D14A
D15A
D0A
D1A
12
3
14
15
16
17
18
30
31
32
tDSDOBUSYL
tSSDISCK
tHSDISCK
tBUSYLH
tCONV
tHOLD
tHSDO
tDSDO
tSCKL
tSCKH
tSCKCH
tCNVL
tCYC
CONVERT
ACQUIRE
POWER-DOWN
POWER-UP
SCK
CNV
BUSY
CHAIN = OVDD
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