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參數(shù)資料
| 型號(hào)： | DC1500A-C |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 8/24頁(yè) |
| 文件大小： | 0K |
| 描述： | BOARD SAR ADC LTC2391-16 |
| 軟件下載： | QuikEval II System |
| 設(shè)計(jì)資源： | DC1500A Design File DC1500A Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 輸入范圍： | ±4.096 V |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 95mW @ 250kSPS |
| 工作溫度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2391-16 |
| 已供物品： | 板 |
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LTC2391-16
16
239116fa
APPLICATIONS INFORMATION
Parallel Modes
The parallel output data interface is active when the
SER/PAR pin is tied low and when both CS and RD are low.
The output data can be read as a 16-bit word as shown
in Figures 8, 9 and 10 or it can be read as two 8-bit bytes
by using the BYTESWAP pin. As shown in Figure 11, with
the BYTESWAP pin low, the rst eight MSBs are output on
the D15 to D8 pins and the eight LSBs are output on the
D7 to DO pins. When BYTESWAP is taken high, the eight
LSBs now are output on the D15 to D8 pins and the eight
MSBs are output on the D7 to D0 pins.
Serial Modes
The serial output data interface is active when the
SER/PAR pin is tied high and when both CS and RD are
low. The serial output data will be clocked out on the
SDOUT pin when an external clock is applied to the SCLK
pin. Clocking out the data after the conversion will yield
the best performance. With a shift clock frequency of at
least 15MHz, a 250ksps throughput is achieved. The serial
output data changes state on the rising edge of SCLK and
can be captured on the falling edge of SCLK. D15 remains
valid till the rst rising edge of shift clock after the rst
falling edge of shift clock. The non-active digital outputs
are high impedance when operating in the serial mode.
If CS and RD are used to gate the serial output data, the
full conversion result should be read before CS and RD
are returned to a high level.
The SDIN input pin is used to daisy chain multiple con-
verters. This is useful for applications where hardware
constraints may limit the number of lines needed to
interface to a large number of converters. For example,
if two devices are cascaded, the MSB of the rst device
will appear at the output after 17 SCLK cycles. The rst
MSB is clocked in on the falling edge of the rst SCLK.
See Figure 12.
Data Format
When OB/2C is high, the digital output is offset binary.
When low, the MSB is inverted resulting in two’s comple-
ment output. This pin is active in both the parallel and
serial modes of operation.
Reset
When the RESET pin is high, the LTC2391-16 is reset, and
if this occurs during a conversion, the conversion is halted
and the data bus is put into Hi-Z mode. In reset, requests
for new conversions are ignored. Once RESET returns low,
the LTC2391-16 is ready to start a new conversion after
the acquisition time plus 2μs has been met. See Figure 13.
Figure 8. Read the Parallel Data Continuously.
The Data Bus is Always Driven and Can’t Be Shared
CS = RD = 0
t4
t6
t16
tCONV
CNVST
BUSY
DATA BUS D[15:0]
PREVIOUS CONVERSION
NEW
239116 F08
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