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參數(shù)資料
| 型號(hào)： | DC1500A-C |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 7/24頁(yè) |
| 文件大小： | 0K |
| 描述： | BOARD SAR ADC LTC2391-16 |
| 軟件下載： | QuikEval II System |
| 設(shè)計(jì)資源： | DC1500A Design File DC1500A Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 輸入范圍： | ±4.096 V |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 95mW @ 250kSPS |
| 工作溫度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2391-16 |
| 已供物品： | 板 |
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LTC2391-16
15
239116fa
APPLICATIONS INFORMATION
= low is applied. In this mode, power consumption drops
to a typical value of 175μW from 95mW. This mode can
be used if the LTC2391-16 is inactive for a long period of
time and the user wants to minimize the power dissipation.
Recovery from Power Shutdown Mode
Once the PD pin is returned to a low level, ending the
power shutdown request, the internal circuitry will begin
to power up. If the internal reference is used, the 2.6kΩ
output impedance with the 1μF bypass capacitor on the
REFIN/REFOUT pins will be the main time constant for
the power-on recovery time. If an external reference is
used, typically allow 5ms for recovery before initiating a
new conversion.
Power Dissipation vs Sampling Frequency
The power dissipation of the LTC2391-16 will decrease
as the sampling frequency is reduced when nap mode
is activated. See Figure 7. In nap mode, a portion of the
circuitry on the LTC2391-16 is turned off after a conversion
has been completed. Increasing the time allowed between
conversions lowers the average power.
TIMING AND CONTROL
The LTC2391-16 conversion is controlled by CNVST. A
falling edge on CNVST will start a conversion. CS and RD
control the digital interface on the LTC2391-16. When
either CS or RD is high, the digital outputs are high
impedance.
CNVST Timing
The LTC2391-16 conversion is controlled by CNVST. A
falling edge on CNVST will start a conversion. Once a
conversion has been initiated, it cannot be restarted until
the conversion is complete. For optimum performance
CNVST should be a clean low jitter signal. Converter status
is indicated by the BUSY output which remains high while
the conversion is in progress. To ensure no errors occur
in the digitized results return the rising edge either within
40ns from the start of the conversion or wait until after
the conversion has been completed. The CNVST timing
needed to take advantage of the reduced power mode of
operation is described in the Nap Mode section.
Internal Conversion Clock
The LTC2391-16 has an internal clock that is trimmed
to achieve a maximum conversion time of 2500ns. No
external adjustments are required and with a maximum
acquisition time of 1485ns, a throughput performance of
250ksps is guaranteed.
DIGITAL INTERFACE
The LTC2391-16 allows both parallel and serial digital
interfaces. The exible OVP supply allows the LTC2391-16
to communicate with any digital logic operating between
1.8V and 5V, including 2.5V and 3.3V systems.
Figure 7. Power Dissipation of the LTC2391-16
Decreases with Decreasing Sampling Frequency
SAMPLING FREQUENCY (kHz)
10
POWER
SUPPL
Y
CURRENT
(mA)
20
30
5
15
25
0.1
10
100
1000
239116 G15
0
1
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