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參數(shù)資料
| 型號： | DAC8426FP |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 8BIT QUAD 10VREF 20-DIP |
| 產品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 18 |
| 設置時間： | 3µs |
| 位數(shù)： | 8 |
| 轉換器數(shù)目： | 4 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 210mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 20-DIP（0.300"，7.62mm） |
| 供應商設備封裝： | 20-PDIP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 4 電流，單極；4 電流，雙極 |
| 采樣率（每秒）： | 333k |
DAC8426
–10–
REV. C
Figure 6. Bipolar Operation
CONNECTION AND LAYOUT GUIDELINES
Layout and design techniques used in the interface between dig-
ital and analog circuitry require special attention to detail. The
following considerations should be evaluated prior to PCB layout.
1. Return signal paths through the ground system should be
carefully considered. High-speed digital logic current pulses
traveling on return ground traces generate glitches that can be
radiated to the analog circuits if the ground path layout pro-
duces loop antennas. Ground planes can minimize this situa-
tion. Separate digital and analog grounding areas to minimize
crosstalk. Ideally a single common-point ground should be on
the same PCB board as the DAC8426. The analog ground re-
turns should take advantage of the appropriate placement of
power supply bypass capacitors.
2. For optimum performance, bypass VDD and VSS (if using
negative supply voltage) with 0.1
F ceramic disk capacitors
to shunt high-frequency spikes. Also use in parallel 6.8
F to
10
F capacitors to provide a charge reservoir for lower fre-
quency load change requirements. The reference output
(VREFOUT) should be bypassed with a 10 F tantalum ca-
pacitor to optimize reference output stability during data in-
put changes. This helps to minimize digital crosstalk.
Table III. Bipolar Output Voltage as a Function of Digital
Input Code
Digital Input
Analog Output
Code
Voltage (= D/256
× 10 V)
255
9.922 V
Full-Scale (FS)
254
9.844 V
FS-1 LSB
129
0.078 V
128
0.000 V
Zero-Scale
127
–0.078 V
1
–9.922 V
0
–10.000 V
Neg Full-Scale
Figure 7. AGND Biasing Scheme Providing Offset Output
Range
3. Power Supply Sequencing—No special requirements exist
with the DAC8426. However, users should be aware that of-
ten the 5 V logic supply may be powered up momentarily
prior to the +15 V analog supply. In this situation, the
DAC8426 ESD input protection diodes will forward bias if
the applied input logic is at logic “1”. No damage will result
to the input since the DAC8426 is designed to withstand mo-
mentary currents of up to 130 mA. This situation will likely
exist for any DAC or ADC operating from a separate analog
supply.
4. ESD input protection—Attention has been given in the de-
sign of the DAC8426 to ESD sensitivity. Using the human
body model test technique (MIL-STD 3015.4) the DAC8426
generally will withstand 1500 V ESD transients on all pins.
Handling and testing prior to PCB insertion generally exposes
ICs to the toughest environment they will experience. Once
the IC is soldered in the PCB, it is still important to consider
any traces that connect to PCB edge connectors. These traces
should be protected with appropriate devices especially if the
boards will experience field replacement or adjustment. Han-
dling the exposed edge connectors by field maintenance
people in a low humidity environment can produce 20 kV
ESD transients which will be detrimental to almost any inte-
grated IC connected to the edge connector.
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