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參數(shù)資料
| 型號： | DAC8426FP |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 8BIT QUAD 10VREF 20-DIP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 18 |
| 設置時間： | 3µs |
| 位數(shù)： | 8 |
| 轉換器數(shù)目： | 4 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 210mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 20-DIP（0.300"，7.62mm） |
| 供應商設備封裝： | 20-PDIP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 4 電流，單極；4 電流，雙極 |
| 采樣率（每秒）： | 333k |
DAC8426
–7–
REV. C
PARAMETER DEFINITIONS
TOTAL UNADJUSTED ERROR (TUE)
This specification includes the Full-Scale-Error, Relative Accu-
racy Zero-Code-Error and the internal reference voltage. The
ideal Full-Scale output voltage is 10 V minus 1 LSB which
equals 9.961 volts. Each LSB equals 10 V
× (1/256) = 0.039 volts.
DIGITAL CROSSTALK
Digital crosstalk is the signal coupled to the output of a DAC
due to a changing digital input from adjacent DACs being up-
dated. It is specified in nano-Volt-seconds (nVs).
CIRCUIT DESCRIPTION
The DAC8426 is a complete quad 8-bit D/A converter. It con-
tains an internal bandgap reference, four voltage switched R-2R
ladder DACs, four DAC latches, four output buffer amplifiers,
and an address decoder. All four DACs share the internal ten
volt reference and analog ground(AGND). Figure 1 provides an
equivalent DAC plus buffer schematic.
Figure 1. Simplified Circuit Configuration for One DAC.
(Switches Are Shown for All “1s” on the Digital Inputs.)
The eleven digital inputs are compatible with both TTL and 5 V
(or higher) CMOS logic. Table I shows the DAC control logic
truth table for WR, A1, and A0 operation. When WR is active
low the input latch of the selected DAC is transparent, and the
DAC’s output responds to the data present on the eight digital
data inputs (DBx). The data (DBx) is latched into the ad-
dressed DAC’s latch on the positive edge of the WR control sig-
nal. The important timing requirements are shown in the Write
Cycle Timing Diagram, Figure 2.
INTERNAL 10 VOLT REFERENCE
The internal 10 V bandgap reference of the DAC8426 is trimm-
ed to the output voltage and temperature drift specifications.
This internal reference is connected to the reference inputs of
the four internal 8-bit D/A converters. The output terminal of
the internal 10 V reference is available on pin 4. The 10 V out-
put of the reference is produced with respect to the AGND pin.
This reference output can be used to supply as much as 5 mA of
additional current to external devices. Care has been taken in
Table I. DAC Control Logic Truth Table
Logic Control
DAC8426
WR
A1
A0
Operation
H
X
No Operation
Device Not Selected
L
DAC A Transparent
g
L
DAC A Latched
L
H
DAC B Transparent
g
L
H
DAC B Latched
L
H
L
DAC C Transparent
g
H
L
DAC C Latched
L
H
DAC D Transparent
g
H
DAC D Latched
L = Low State, H = High State, X = Don’t Care
Figure 2. Write Cycle Timing Diagram
the design of the internal DAC switching to minimize transients
on the reference voltage terminal (VREFOUT). Other devices
connected to this reference terminal should have well behaved
input loading characteristics. D/A converters such as the PMI
PM7226A have been designed to minimize reference input tran-
sient currents and can be directly connected to the DAC8426
10 V reference. Devices exhibiting large current transients due
to internal switching should be buffered with an op amp to
maintain good overall system noise performance. A 10
F refer-
ence output bypass capacitor is required.
BUFFER AMPLIFIER SECTION
The four internal unity-gain voltage buffers provide low output
impedance capable of sourcing 5 mA or sinking 350
A. Typical
output slew rates of
±4 V/s are achieved with 10 V full-scale out-
put changes and RL = 2 k
. Figure 3 photographs show large sig-
nal and settling time response. Capacitive loads to 3300 pF
maximum, and resistive loads to 2 k
minimum can be applied.
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