
DAC1617D1G0
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1.1 — 30 September 2011
48 of 66
NXP Semiconductors
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
3
MDS_PRERUN_ENA
R/W
automatic MDS start-up
no mds_win/mds_ref generation in advance
mds_win/mds_ref run-in before mds_evaluation
width of MDS (in output clock -periods)
1 DAC clock period
2 DAC clock periods
(mds_pulsewidth
1)
4 DAC clock periods
0
1
2 to 0
MDS_PULSEWIDTH[2:0]
R/W
000
001
010 to 111
Table 38.
Default values are shown highlighted.
Bit
Symbol
MDS_MISCCNTRL0 register (address 03h) bit description
…continued
Access
Value
Description
Table 39.
Default values are shown highlighted.
Bit
Symbol
7
MDS_MAN
MDS_MAN_ADJUSTDLY register (address 04h) bit description
Access
R/W
Value
Description
adjustment delays mode
auto-control adjustment delays
manual control adjustment delays
adjustment delay value
if MDS_MAN = 0 then initial value adjustment delay
if MDS_MAN = 1 then controls adjustment delay
0
1
6 to 0
MDS_MAN_ADJUSTDLY[6:0] R/W
-
-
Table 40.
Default values are shown highlighted.
Bit
Symbol
7 to 0
MDS_AUTO_CYCLES[7:0]
MDS_AUTO_CYCLES register (address 05h) bit description
Access
R/W
Value
-
Description
number of evaluation cycles applied for MDS. If set to
255 then IC continuously generates/monitors the MDS
pulse
Table 41.
Default values are shown highlighted.
Bit
Symbol
7
MDS_SR_CKEN
MDS_MISCCNTRL1 register (address 06h) bit description
Access
R/W
Value
-
0
1
Description
lock mode
free-running MDS_SR_CKEN
MDS_SR_CKEN forced low
lockout detector soft reset
MDS_SR_LOCKOUT in use
MDS_SR_LOCKOUT forced low
lock detector soft reset
MDS_SR_LOCK in use
MDS_SR_LOCK forced low
relock mode
no action
relock when lockout occurs
number of succeeding 'equal' detections until lock
6
MDS_SR_LOCKOUT
R/W
0
1
5
MDS_SR_LOCK
R/W
0
1
4
MDS_RELOCK
R/W
0
1
-
3 to 0
MDS_LOCK_DELAY[3:0]
R/W