參數(shù)資料
型號(hào): DAC1205D750HW
廠商: NXP Semiconductors N.V.
元件分類: 外設(shè)及接口
英文描述: Dual 12-bit DAC, up to 750 Msps; 2x 4x and 8x interpolating
封裝: DAC1205D750HW/C1<SOT638-1 (HTQFP100)|<<http://www.nxp.com/packages/SOT638-1.html<1<Always Pb-free,;DAC1205D750HW/C1<SOT638-1 (HTQFP100)|<<http://www.nxp.com/packages/SOT6
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代理商: DAC1205D750HW
DAC1205D750
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 June 2011
22 of 42
NXP Semiconductors
DAC1205D750
Dual 12-bit DAC, up to 750 Msps; 4x and 8x interpolating
10.2.5
Recommended configuration
It is recommended that the following additional settings are used to obtain optimum
performance at up to 750 Msps
Table 31.
Address
Dec
17
19
20
10.3 Input data
The setting applied to MODE_SEL (register 00h[3]; see
Table 10 on page 17
) defines
whether the DAC1205D750 operates in the Dual-port mode or in Interleaved mode (see
Table 32
).
Table 32.
Bit 3 setting
0
1
10.3.1
Dual-port mode
The data input for Dual-port mode operation is shown in
Figure 5 “Dual-port mode”
. Each
DAC has its own independent data input. The data enters the input latch on the rising
edge of the internal clock signal and is transferred to the DAC latch.
10.3.2
Interleaved mode
The data input for the Interleaved mode operation is illustrated in
Figure 6 “Interleaved
mode operation”
.
Recommended configuration
Value
Bin
00001010
01101100
01101100
Hex
11h
13h
14h
Dec
10
108
108
Hex
0Ah
6Ch
6Ch
Mode selection
Function
Dual port mode
Interleaved mode
I11 to I0
active
active
Q11 to Q0
active
off
Pin 41
Q11
SELIQ
Fig 5.
Dual-port mode
001aam195
LATCH
I
2
×
2
×
2
×
I11 to I0
FIR 1
FIR 1
FIR 2
FIR 2
FIR 3
FIR 3
LATCH
Q
2
×
2
×
2
×
Q11 to Q0
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