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參數(shù)資料
| 型號： | CYW173SXC |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 3/5頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK GEN TAPE DRV 4CH 16SOIC |
| 標準包裝： | 48 |
| 類型： | 時鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | CPB Tape Drive System |
| 輸入： | 晶體 |
| 輸出： | TTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:4 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 100MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
W173
......... Document #: 38-07313 Rev. *B Page Page 3 of 5 of 5
Power Supply Connections
The recommended single voltage power supply configuration
for the W173 is shown schematically in Figure 1. These recom-
mendations should be followed to both ensure adequate
device performance and to control EMI. The major consider-
ations can be summarized as follows:
1. Decoupling Capacitor—A 0.1-F decoupling capacitor
should be used for each VDD pin to minimize crosstalk be-
tween output frequencies. The trace to the VDD pin and to
the ground via should be as short as possible.
2. Ferrite Bead (FB)—A common supply connection should
be used for all W173 VDD pins. A ferrite bead should be
used on this common supply as shown to remove high
frequency system noise.
3. 22-F Supply Filter Capacitor—The 22-F capacitor filters
low frequency supply noise that may produce clock output
jitter. Depending on the particular application, this capacitor
may not be required; its use should be considered optional.
Mounting pads should be implemented in PCB layout. Use
of this capacitor in production should be determined upon
prototype evaluation.
4. PCB power supply traces should be at least 20 mils wide to
assure adequate trade impedance recommend Power
Supply Schematic–Single Voltage Supply Operation.
Ground Connections
All ground connections should be made to the main system
ground plane. These connections should be as short as
possible. No cuts should be made in the ground plane around
the clock device since this can increase system EMI and
reduce clock performance.
Clock Output Lines
1. The clock line width should be set to provide a 60
trace
impedance. This width will vary depending on the PCB ma-
terial; the PCB supplier can suggest what width to use for
a 60
clock line. In general, an 8-mil trace will provide a
60
impedance on a multi-level board.
2. The series termination resistor (sometimes called “damping
resistor”) must be placed in series with the clock line as
close to the clock output as possible (within one inch).
3. Assume an output resistance from the W173 of 40
,
choose series resistors appropriate to the number of driven
traces.
VDD
6.6MHz
GND
13.2MHz
VDD
10MHz
VDD
16
15
14
13
12
11
10
9
VDD
X1
X2
GND
OE
VDD
50MHz
GND
1
2
3
4
5
6
7
8
0.1 F
22 F
C1
FB
System VDD
W173
GND
0.1 F
Figure 1. Test Circuit
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYW173SXCT | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Tape Media Backup Dr Clk Gen W173 DS RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| CYW180-01SX | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Peak Reducing EMI Solution |
| CYW180-01SXT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Peak Reducing EMI Solution |
| CYW180-02SX | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Peak Reducing EMI Solution |
| CYW180-02SXT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Peak Reducing EMI Solution |
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