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參數(shù)資料
| 型號(hào)： | CYW173SXC |
| 廠商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 2/5頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK GEN TAPE DRV 4CH 16SOIC |
| 標(biāo)準(zhǔn)包裝： | 48 |
| 類(lèi)型： | 時(shí)鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | CPB Tape Drive System |
| 輸入： | 晶體 |
| 輸出： | TTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:4 |
| 差分 - 輸入:輸出： | 無(wú)/無(wú) |
| 頻率 - 最大： | 100MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類(lèi)型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
W173
......... Document #: 38-07313 Rev. *B Page Page 2 of 5 of 5
Note:
1. All inputs, except X1 or X2, have an internal pull-up resistor. Unconnected inputs will assume a logic HIGH condition.
Pin Definitions [1]
Pin Name
Pin No.
Pin Type
Pin Description
OE
5
I
Output Enable: When LOW, this input signal puts all outputs into a high-impedance
state.
13.2MHZ
13
O
Clock Output: Provides a TTL-level timing signal proportional in frequency to the
input signal. For a 26.5625 MHz reference, the frequency will be 13.2 MHz.
6.6MHZ
15
O
Clock Output: Provides a TTL-level timing signal proportional in frequency to the
input signal. For a 26.5625 MHz reference, the frequency will be 6.6 MHz.
10MHZ
10
O
Clock Output: Provides a TTL-level timing signal proportional in frequency to the
input signal. For a 26.5625 MHz reference, the frequency will be 10.0 MHz.
50MHZ
7
O
Clock Output: Provides a TTL-level timing signal proportional in frequency to the
input signal. For a 26.5625 MHz reference, the frequency will be 50.0 MHz.
X1
2
I
External Crystal Connection: This pin has dual functions. It can be used as an
external 26.5625 MHz crystal connection or as an external reference frequency
input.
X2
3
O
External Crystal Connection: An input connection for an external 26.5625 MHz
crystal. If using an external reference, this pin must be left unconnected.
VDD
1, 6, 9, 12, 16
P
Power Supply Connections: Connect both VDD pins to the same voltage, either
3.3V or 5.0V. Each VDD pin should have a decoupling capacitor (such as 0.1 F)
placed as close to the pin as possible.
GND
4, 8, 11, 14
G
Ground Connections: Connect all ground pins to the common system ground
plane.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYW173SXCT | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Tape Media Backup Dr Clk Gen W173 DS RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| CYW180-01SX | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:Peak Reducing EMI Solution |
| CYW180-01SXT | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:Peak Reducing EMI Solution |
| CYW180-02SX | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:Peak Reducing EMI Solution |
| CYW180-02SXT | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:Peak Reducing EMI Solution |
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