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參數(shù)資料
| 型號： | CYW150OXCT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 11/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK 440BX AGP 56SSOP |
| 標準包裝： | 1,000 |
| 類型： | 時鐘/頻率合成器，擴展頻譜時鐘發(fā)生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服務器 |
| 輸入： | 時鐘，晶體 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:33 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 150MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-BSSOP（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 56-SSOP |
| 包裝： | 帶卷 (TR) |
CYW150
........................ Document #: 38-07177 Rev. *B Page 6 of 14
Writing Data Bytes
Each bit in Data Bytes 0–7 control a particular device function
except for the “reserved” bits which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit 7.
Table 5 gives the bit formats for registers located in Data Bytes
0–7.
Table 6 details additional frequency selections that are
available through the serial data interface.
Table 7 details the select functions for Byte 0, bits 1 and 0.
4
Data Byte 0
Refer to Table 5 The data bits in Data Bytes 0–5 set internal CYW150 registers that control device
operation. The data bits are only accepted when the Address Byte bit sequence is
11010010, as noted above. For description of bit control functions, refer to Table 5,
Data Byte Serial Configuration Map.
5
Data Byte 1
6
Data Byte 2
7
Data Byte 3
8
Data Byte 4
9
Data Byte 5
10
Data Byte 6
Don’t Care
Unused by the CYW150, therefore bit values are ignored (Don’t Care).
11
Data Byte 7
Table 4. Byte Writing Sequence (continued)
Byte
Sequence
Byte Name
Bit Sequence
Byte Description
Table 5. Data Bytes 0–5 Serial Configuration Map
Bit(s)
Affected Pin
Control Function
Bit Control
Default
Pin No.
Pin Name
0
1
Data Byte 0
7–
–
(Reserved)
–
0
6
–
SEL_2
See Table 6
0
5
–
SEL_1
See Table 6
0
4
–
SEL_0
See Table 6
0
3
–
Frequency Table Selection
Frequency
Controlled by FS
(3:0) Table 2
Frequency
Controlled by SEL
(3:0) Table 6
0
2
–
SEL3
Refer to Table 6
0
1–0
–
Bit 1
Bit 0
Function (See Table 7 for function details)
0
Normal Operation
0
1
(Reserved)
1
0
Spread Spectrum On
1
All Outputs Three-stated
00
Data Byte 1
7–
–
0
6–
–
0
5–
–
0
4–
–
0
3
46
SDRAM_F
Clock Output Disable
Low
Active
1
2
49
CPU2
Clock Output Disable
Low
Active
1
51
CPU1
Clock Output Disable
Low
Active
1
0
52
CPU_F
Clock Output Disable
Low
Active
1
Data Byte 2
7–
–
(Reserved)
–
0
6
8
PCI_F
Clock Output Disable
Low
Active
1
5
16
PCI5
Clock Output Disable
Low
Active
1
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