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參數(shù)資料
| 型號： | CY7C4205-10ACT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | FIFO |
| 英文描述： | 256 X 18 OTHER FIFO, 8 ns, PQFP64 |
| 封裝： | 14 X 14 MM, PLASTIC, TQFP-64 |
| 文件頁數(shù)： | 22/25頁 |
| 文件大?。?/td> | 412K |
| 代理商： | CY7C4205-10ACT |
CY7C4425/4205/4215
CY7C4225/4235/4245
6
tPAFsynch
Clock to Programmable Almost-Full Flag
(Synchronous mode, VCC/SMODE tied to VSS)
8
10
15
20
ns
tPAEasynch
Clock to Programmable Almost-Empty Flag[12]
(Asynchronous mode, VCC/SMODE tied to VCC)
12
16
20
25
ns
tPAEsynch
Clock to Programmable Almost-Full Flag
(Synchronous mode, VCC/SMODE tied to VSS)
8
10
15
20
ns
tHF
Clock to Half-Full Flag
12
16
20
25
ns
tXO
Clock to Expansion Out
7
10
15
20
ns
tXI
Expansion in Pulse Width
3
6.5
10
14
ns
tXIS
Expansion in Set-Up Time
4.5
5
10
15
ns
tSKEW1
Skew Time between Read Clock and Write
Clock for Full Flag
5
6
10
12
ns
tSKEW2
Skew Time between Read Clock and Write
Clock for Empty Flag
5
6
10
12
ns
tSKEW3
Skew Time between Read Clock and Write
Clock for Programmable Almost Empty and Pro-
grammable Almost Full Flags.
10
15
18
20
ns
Switching Characteristics Over the Operating Range (continued)
Parameter
Description
7C42X5-10
7C42X5-15
7C42X5-25
7C42X5-35
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Switching Waveforms
Notes:
10. Pulse widths less than minimum values are not allowed.
11.
Values guaranteed by design, not currently tested.
12. PAFasynch, tPAEasynch, after program register write will not be valid until 5 ns + tPAF(E).
13. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the
rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.
Write Cycle Timing
tCLKH
tCLKL
NO OPERATION
tDS
tSKEW1
tENS
WEN
tCLK
tDH
tWFF
tENH
WCLK
D0 –D17
FF
REN
RCLK
42X5–6
[13]
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| CY7C4241-35JC | 4K X 9 OTHER FIFO, 20 ns, PQCC32 |
| CY7C4421-15JIT | 64 X 9 OTHER FIFO, 10 ns, PQCC32 |
| CY7C4421-25AC | 64 X 9 OTHER FIFO, 15 ns, PQFP32 |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C4205-10AXC | 功能描述:先進先出 256x18 IDT Compat SYNC 先進先出 COM RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| CY7C4205-10AXCT | 功能描述:先進先出 256x18 IDT Compat SYNC 先進先出 COM RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| CY7C4205-15AC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C4205-15ACT | 制造商:Cypress Semiconductor 功能描述: |
| CY7C4205-15ASC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 256 x 18 64-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:256 X 18 68 PIN IDT COMPAT SYNC FIFO - Bulk |
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