參數(shù)資料
型號: CY7C4205-10ACT
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: FIFO
英文描述: 256 X 18 OTHER FIFO, 8 ns, PQFP64
封裝: 14 X 14 MM, PLASTIC, TQFP-64
文件頁數(shù): 2/25頁
文件大?。?/td> 412K
代理商: CY7C4205-10ACT
CY7C4425/4205/4215
CY7C4225/4235/4245
10
Notes:
19. PAE offset – n. Number of data words into FIFO already = n.
20. PAE offset – n.
21. tSKEW3 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the
rising RCLK is less than tSKEW3, then PAE may not change state until the next RCLK.
22. If a read is performed on this rising edge of the read clock, there will be Empty + (n – 1) words in the FIFO when PAE goes LOW.
Switching Waveforms (continued)
tENH
Programmable Almost Empty Flag Timing
WCLK
PAE]
REN
RCLK
tCLKH
tPAE
tENS
n+1 WORDS
IN FIFO
tCLKL
tENS
tPAE
n WORDS IN FIFO
42X5–13
[19]
WEN
Note
tENH
WCLK
PAE
RCLK
tCLKH
tENS
tCLKL
tENS
tPAEsynch
N + 1 WORDS
INFIFO
42X5–14
tENH
tENS
tENH
tENS
tPAEsynch
REN
WEN
WEN2
tSKEW3
Note
Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW)
[21]
22
20
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