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| 型號(hào)： | CY7C028V-20ACT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 3.3V 32K/64K x 16/18 Dual-Port Static RAM |
| 中文描述： | 64K X 16 DUAL-PORT SRAM, 20 ns, PQFP100 |
| 封裝： | PLASTIC, MS-026, TQFP-100 |
| 文件頁(yè)數(shù)： | 21/22頁(yè) |
| 文件大?。?/td> | 635K |
| 代理商： | CY7C028V-20ACT |
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CY7C027V/027AV/028V
CY7C037AV/038V
Document #: 38-06078 Rev. *D
Page 8 of 22
Figure 3. AC Test Loads and Waveforms
3.0V
GND
90%
10%
3ns
3 ns
10%
ALL INPUT PULSES
(a) Normal Load (Load 1)
R1 = 590
3.3 V
OUTPUT
R2 = 435
C= 30 pF
VTH = 1.4 V
OUTPUT
C= 30 pF
(b) Thévenin Equivalent (Load 1)
(c) Three-State Delay(Load 2)
R1 = 590
R2 = 435
3.3 V
OUTPUT
C= 5pF
RTH = 250
including scope and jig)
(Used for tLZ, tHZ, tHZWE, & tLZWE
Switching Characteristics Over the Operating Range[12]
Parameter
Description
CY7C027V/027AV/028V/
CY7C037AV/CY7C038V
Unit
-15
-20
-25
Min
Max
Min
Max
Min
Max
Read Cycle
tRC
Read cycle time
15
–
20
–
25
–
ns
tAA
Address to data valid
–
15
–
20
–
25
ns
tOHA
Output hold from address change
3
–
3
–
3
–
ns
tACE[13]
CE LOW to data valid
–
15
–
20
–
25
ns
tDOE
OE LOW to data valid
–10
–
12–13
ns
tLZOE[14, 15, 16]
OE LOW to Low Z
3
–3
–
ns
tHZOE[14, 15, 16]
OE HIGH to High Z
–
10
–
12
–
15
ns
CE LOW to Low Z
3
–
3
–
3
–
ns
tHZCE[14, 15, 16]
CE HIGH to High Z
–
10
–12–15
ns
tPU[16]
CE LOW to power-up
0
–
0
–
0
–
ns
tPD[16]
CE HIGH to power-down
–
15
–
20
–
25
ns
tABE[13]
Byte enable access time
–
15
–
20
–
25
ns
Write Cycle
tWC
Write cycle time
15
–
20
–
25
–
ns
tSCE[13]
CE LOW to write end
12
–
16
–
20
–
ns
tAW
Address valid to write end
12
–
16
–
20
–
ns
tHA
Address hold from write end
0
–
0
–
0
–
ns
tSA[13]
Address setup to write start
0
–
0
–
0
–
ns
tPWE
Write pulse width
12–17–22–
ns
tSD
Data setup to write end
10–12–15–
ns
Notes
12. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified
IOI/IOH and 30 pF load capacitance.
13. To access RAM, CE=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire tSCE time.
14. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
15. Test conditions used are Load 2.
16. This parameter is guaranteed by design, but it is not production tested. For information on port-to-port delay through RAM cells from writing port to reading port,
refer to Figure 11.
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