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參數(shù)資料
| 型號(hào)： | CY28551LFXC-3T |
| 廠商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 5/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK INTEL/AMD SIS VIA 56QFN |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | 時(shí)鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU，AMD CPU |
| 輸入： | 晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:20 |
| 差分 - 輸入:輸出： | 無(wú)/是 |
| 頻率 - 最大： | 400MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-VFQFN 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 56-QFN（8x8） |
| 包裝： | 帶卷 (TR) |
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CY28551-3
....................Document #: 001-05677 Rev. *D Page 13 of 28
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
CL ................................................... Crystal load capacitance
CLe .........................................Actual loading seen by crystal
using standard value trim capacitors
Ce .....................................................External trim capacitors
Cs ............................................. Stray capacitance (terraced)
Ci .......................................................... Internal capacitance
(lead frame, bond wires etc.)
Multifunction Pin Selection
In CY28551-3, some of the pins can provide different types of
frequency, depending on the SEL[1:0] HW strapping pin
setting, to support different chipset vendors. The configuration
is shown as follows:
Dynamic Frequency
Dynamic Frequency - Dynamic Frequency (DF) is a technique
to increase CPU frequency or SRC frequency dynamically
from any starting value. The user selects the starting point,
either by HW, FSEL, or DAF, then enables DF. After that, DF
will dynamically change as determined by DF-N registers.
DF Pin - There are two pins to be used for Dynamic Frequency
(DF). When used as DF, these two pins will map to four DF-N
registers that correspond to different “N” values for Dynamic
Frequency. Any time there is a change in DF, it should load the
new value.
DF_EN bit - This bit enables the DF mode. By default, it is not
set. When set, the operating frequency is determined by
DF[2:0] pins. Default = 0, (No DF)
Dial-A-Frequency (CPU & PCIEX)
This feature allows the user to over clock their system by
slowly stepping up the CPU or SRC frequency. When the
programmable output frequency feature is enabled, the CPU
and SRC frequencies are determined by the following
equation:
Fcpu = G * N/M or Fcpu=G2 * N, where G2 = G/M.
“N” and “M” are the values programmed in Programmable
Frequency Select N-Value Register and M-Value Register,
respectively. “G” stands for the PLL Gear Constant, which is
determined by the programmed value of FS[E:A]. See
Figure 1 for the Gear Constant for each Frequency selection.
The PCI Express only allows user control of the N register, the
M value is fixed and documented in Figure 1.
In this mode, the user writes the desired N and M value into
the DAF I2C registers. The user cannot change only the M
value and must change both the M and the N values at the
same time, if they require a change to the M value. The user
may change only the N value if required.
XTAL
Ce2
Ce1
Cs1
Cs2
X1
X2
Ci1
Ci2
Clock Chip
Trace
2.8 pF
Trim
33 pF
Pin
3 to 6p
Figure 2. Crystal Loading Example
Load Capacitance (each side)
Total Capacitance (as seen by the crystal)
Ce = 2 * CL – (Cs + Ci)
Ce1 + Cs1 + Ci1
1
+
Ce2 + Cs2 + Ci2
1
()
1
=
CLe
Table 6.
SEL[1:0]
LINK/DOT/SA
TA
SATA/PCIE
Platform
00
LINK
SATA
SIS
01
DOT
SATA
Intel W/Gfx
10
LINK
PCIEX
VIA
11
SATA
PCIEX
Intel
Table 7.
DOC[2:1]
DOC N register
00
Original Frequency
01
DF1_N
10
DF2_N
11
DF3_N
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28551LFXCT | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Universal System Clk Intel AMD SiS Via RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| CY2862-000 | 制造商:TE Connectivity 功能描述:82A0111-4-9-G110 |
| CY2863-000 | 制造商:TE Connectivity 功能描述:82A0111-8-9-G110 - Bulk |
| CY28800 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:100-MHz Differential Buffer for PCI Express and SATA |
| CY28800OXC | 功能描述:時(shí)鐘緩沖器 PCI Express & Sata Diff Buffer 100MHz RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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