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參數(shù)資料
| 型號： | CY28506OC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | 166.7 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 封裝： | 5.30 MM, SSOP-28 |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 85K |
| 代理商： | CY28506OC |
CY28506
Document #: 38-07295 Rev. **
Page 3 of 9
Byte 0: Frequency Select Register
Bit
@Pup
Pin#
Name
Description
7
0
-
SWEN
If this bit is programmed to a
“
1
”
, the FS frequency and SS operation will be
derived from the register values in bits (0:6) for selecting the frequency and
Spread Spectrum. If this bit is programmed to a
“
0
”
, the FS mode and SS mode
will be derived from the hardware pins on FS(0:2) and SSON. When reading
this register, if bit3 = 1, then the software register is read back and enabled,
and when reading bit3 = 0, then the hardware values are read back and
enabled.
6
H/W Setting
17
SSON
Spread Spectrum Enable: 0 = off, 1 = on. Value is the H/W setting at power-up,
then can be over-written via this bit.
5
0
SSMode
Spread Spectrum Mode Select: 0 = down spread, 1 = center spread
(see
Table 3
)
4
0
S1
Spread Spectrum Table Select 1. (see
Table 3
)
3
0
S0
Spread Spectrum Table Select 0. (see
Table 3
)
2
H/W Setting
10
FS2
For selecting frequencies in table 1; when SWEN = 1, FS0 = FS1 = FS0 = 1
does not get decoded.
1
H/W Setting
11
FS1
For selecting frequencies in table 1; when SWEN = 1, FS0 = FS1 = FS0 = 1
does not get decoded.
0
H/W Setting
12
FS0
For selecting frequencies in table 1; when SWEN = 1, FS0 = FS1 = FS0 = 1
does not get decoded.
Byte 1: CPU Clock Register
Bit
@Pup
Pin#
Name
Description
7
1
19
CPU3 Dual Drive
1 = high output drive. 0 = low output drive
6
1
21
CPU2 Dual Drive
1 = high output drive. 0 = low output drive
5
1
23
CPU1 Dual Drive
1 = high output drive. 0 = low output drive
4
1
25
CPU0Dual Drive
1 = High output drive. 0 = low output drive
3
1
19
CPU3 Enable
1 = output enabled (running). 0 = output disabled asynchronously in a low state
2
1
21
CPU2 Enable
1 = output enabled (running). 0 = output disabled asynchronously in a low state
1
1
23
CPU1 Enable
1 = output enabled (running). 0 = output disabled asynchronously in a low state
0
1
25
CPU0 Enable
1 = output enabled (running). 0 = output disabled asynchronously in a low state
Byte 2
: Dial-a-Frequency
Control Register N
Bit
@Pup
Pin#
Name
Description
7
0
Reserved
6
0
N6, MSB
These bits are for the PLL
’
s internal N register. This access allows the user to
modify the CPU frequency at very high resolution (accuracy).
5
0
N5
4
0
N4
3
0
N3
2
0
N2
1
0
N1
0
0
N0, LSB
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28506OCT | 制造商:Rochester Electronics LLC 功能描述:CLOC - Tape and Reel |
| CY28507ZC-3 | 功能描述:時(shí)鐘緩沖器 PacketClockClk RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CY28508OCT | 制造商:Cypress Semiconductor 功能描述: |
| CY28508OXC | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Power PC RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| CY28508OXCT | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Power PC RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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