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參數(shù)資料
| 型號(hào)： | CY28506OC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | 166.7 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 封裝： | 5.30 MM, SSOP-28 |
| 文件頁數(shù)： | 2/9頁 |
| 文件大?。?/td> | 85K |
| 代理商： | CY28506OC |
CY28506
Document #: 38-07295 Rev. **
Page 2 of 9
Pin Description
Pin
Name
PWR
I/O
Description
3
XIN
V
DD
V
DD
I
Oscillator Buffer Input. Connect to a crystal or to an external clock.
4
XOUT
O
Oscillator Buffer Output. Connect to a crystal. Do not connect when an
external clock is applied at XIN.
25, 23, 21, 19
CPU(0:3)
V
DDC
V
DD
V
DD
V
DD
V
DD
V
DD
O
1.8V Host bus clock outputs
12
FS0
PD
Frequency select 0. See
Table 1
. Not latched.
11
FS1
PD
Frequency select 1. See
Table 1
. Not latched.
10
FS2
PD
Frequency select 2. See
Table 1
. Not latched.
17
SSON
PU
0 = Spread OFF, 1 = Spread ON. Not latched.
27
STOP0#
PU
CPU0 stop clock control input. When this signal is at a logic LOW level
(0), CPU0 clock stops at a logic LOW level. Using this pin to start and stop
CPU0 clock ensures synchronous (no short or long clocks) transitioning
of this clock.
28
STOP1#
V
DD48
PU
CPU1 stop clock control input. When this signal is at a logic LOW level
(0), CPU1 clock stops at a logic LOW level. Using this pin to start and stop
CPU1 clock ensures synchronous (no short or long clocks) transitioning
of this clock.
5
STOP2#
V
DD48
PU
CPU2 stop clock control input. When this signal is at a logic LOW level
(0), CPU2 clock stops at a logic LOW level. Using this pin to start and stop
CPU2 clock ensures synchronous (no short or long clocks) transitioning
of this clock.
6
STOP3#
V
DD
PU
CPU3 stop clock control input. When this signal is at a logic LOW level
(0), CPU3 clock stops at a logic LOW level. Using this pin to start and stop
CPU3 clock ensures synchronous (no short or long clocks) transitioning
of this clock.
9
SDATA
V
DD
PU
Serial data input pin. Conforms to the SMBus specification of a Slave
Receive/Transmit device. This pin is an input when receiving data. It is an
open drain output when acknowledging or transmitting data.
8
SCLK
V
DD
PU
Serial clock input pin. Conforms to the SMBus specification.
18, 22, 26
VDDC
1.8V Power for CPU output buffers
20, 24
VSSC
Ground for CPU output buffers
13, 16
VDDA
3.3V Analog Power Supply
14, 15
VSSA
Analog Power Ground
7, 11
VDD
3.3V Common Power Supply
1
VSS
Common Ground pins.
2
VSSX
Common Ground pins.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28506OCT | 制造商:Rochester Electronics LLC 功能描述:CLOC - Tape and Reel |
| CY28507ZC-3 | 功能描述:時(shí)鐘緩沖器 PacketClockClk RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CY28508OCT | 制造商:Cypress Semiconductor 功能描述: |
| CY28508OXC | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Power PC RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| CY28508OXCT | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Power PC RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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