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參數(shù)資料
| 型號： | CY2037AWAF |
| 英文描述： | Crystal Oscillator |
| 中文描述： | 晶體振蕩器 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 208K |
| 代理商： | CY2037AWAF |
CY2037
6
Output Clock Switching Characteristics
Over the Operating Range
[3]
Symbol
t
1w
Description
Output Duty Cycle at
1.4V, V
DD
= 4.5–5.5V
t
1w
= t
1A
÷
t
1B
Test Conditions
Min
45
45
40
40
45
40
40
45
40
Typ
Max
55
55
60
60
55
60
60
55
60
Unit
%
%
%
%
%
%
%
%
%
1–40 MHz, C
L
<= 50 pF
40–66 MHz, C
L
<= 15pF
66–125 MHz, C
L
<= 25pF
125–133 MHz, C
L
<= 15pF
1–66.6 MHz, C
L
<= 25pF
66.6–125 MHz, C
L
<= 25 pF
125–133 MHz, C
L
<= 15pF
1–40 MHz, C
L
<= 30 pF
40–100 MHz, C
L
<= 15pF
t
1x
Output Duty Cycle at
V
DD
/2, V
DD
= 4.5–5.5V
t
1x
= t
1A
÷
t
1B
Output Duty Cycle at
V
DD
/2, V
DD
= 3.0–3.6
t
1y
= t
1A
÷
t
1B
Output Duty Cycle at
V
DD
/2, V
DD
= 2.7–3.0
t
1y
= t
1A
÷
t
1B
Output Clock Rise time
t
1y
t
1z
1–40 MHz, C
L
<= 15pF
40–66.6 MHz, C
L
<= 10pF
40
40
60
60
%
%
t
2
Between 0.8 –2.0V, V
DD
= 4.5V–5.5V, C
L
= 50 pF
Between 0.8 –2.0V, V
DD
= 4.5V–5.5V, C
L
= 25 pF
Between 0.8 –2.0V, V
DD
= 4.5V–5.5V, C
L
= 15 pF
Between 0.2V
DD
– 0.8V
DD
, V
DD
= 4.5V–5.5V, C
L
= 50 pF
Between 0.2V
DD
– 0.8V
DD
, V
DD
= 3.0V–3.6V, C
L
= 30 pF
Between 0.2V
DD
– 0.8V
DD
, V
DD
= 2.7V–3.6V, C
L
= 15 pF
Between 0.8V–2.0V, V
DD
= 4.5V–5.5V, C
L
= 50 pF
Between 0.8 –2.0V, V
DD
= 4.5V–5.5V, C
L
= 25 pF
Between 0.8 –2.0V, V
DD
= 4.5V–5.5V, C
L
= 15 pF
Between 0.2V
DD
– 0.8V
DD
, V
DD
= 4.5V-5.5V, C
L
= 50 pF
Between 0.2V
DD
– 0.8V
DD
, V
DD
= 3.0V–3.6V, C
L
= 30 pF
Between 0.2V
DD
– 0.8V
DD
, V
DD
= 2.7V–3.6V, C
L
= 15 pF
PWR_DWN or OE pin LOW to HIGH
[3]
1.8
1.2
0.9
3.4
4.0
2.4
1.8
1.2
0.9
3.4
4.0
2.4
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
t
3
Output Clock Fall time
t
4
Start-up time out of
power-down
Power Down delay time
(synchronous setting)
Power Down delay time
(asynchronous setting)
Power Up time
Output disable time
(synchronous setting)
Output disable time
(asynchronous setting)
Output enable time
(always synchronous
enable)
Peak-to-Peak Period
Jitter
1
t
5a
PWR_DWN pin LOW to output LOW
(T=period of Output clk)
PWR_DWN pin LOW to output LOW
T/2
T+10
ns
t
5b
10
15
ns
t
6
t
7a
From power on
[3]
OE pin LOW to output Hi-Z
(T=period of output clk)
OE pin LOW to output Hi-Z
1
2
ms
ns
T/2
T+10
t
7b
10
15
ns
t
8
PWR_DWN or OE pin LOW to HIGH
(T=period of output clk)
T
1.5T+25
ns
t
9
V
DD
= 4.5V–5.5V, Fo > 33 MHz, VCO > 100 MHz
V
DD
= 2.7V–3.6V, Fo > 33 MHz, VCO >100 MHz
V
DD
= 2.7V–5.5V, Fo <33 MHz
±100
±125
±250
±125
±200
1% of F
O
ps
ps
ps
Note:
3.
4.
Oscillator start time cannot be guaranteed for all crystal types. This specification is for operation with AT cut crystals with ESR < 70 ohms.
Not all parameters measured in production testing.
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