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參數(shù)資料
| 型號： | CX72301-11 |
| 廠商： | SKYWORKS SOLUTIONS INC |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 1000 MHz, PDSO28 |
| 封裝： | EXPOSED PAD, TSSOP-28 |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 165K |
| 代理商： | CX72301-11 |
DATA SHEET CX72301
Skyworks Solutions, Inc. Phone [781] 376-3000 Fax [781] 376-3100 sales@skyworksinc.com www.skyworksinc.com
101090H Skyworks Proprietary and Confidential information Products and Product Information are Subject to Change Without Notice July 21, 2004
5
Fractional-N Applications. The desired division ratio for the
main and auxiliary synthesizer is given by the following equation:
N
f rac ti on al
F
VC O
F
di v_ref
-------------------
=
where Nfractional must be between 37.5 and 537.5.
The value to be programmed in the Main or Auxiliary Divider
Register is given by the equation:
N
reg
R ound N
f r act io nal
32
–
=
NOTE: The Round function rounds the number to the nearest
integer.
When in fractional mode, allowed values for Nreg are from 6 to
505, inclusive.
The value to be programmed in the Main or Auxiliary Dividend
Register is given by the following equation:
di v i de nd
R ound divi der
N
f ra ct io nal
N
reg
32
–
=
where the divider is either 1024 in 10-bit mode or 262144 in
18-bit mode. Therefore, the dividend is a signed binary value
either 10 or 18 bits long.
NOTE: Because of the high fractionality of the CX72301, there is
no practical need for any integer relationship between
the reference frequency and the channel spacing or
desired VCO frequencies.
Sample calculations for two fractional-N applications are provided
in Figure 4.
Case 1: To achieve a desired Fvco_main frequency of 902.4530 MHz using a crystal frequency of 40 MHz with operation
of the synthesizer in 18-bit mode. Since the maximum internal reference frequency (Fdiv_ref) is 25 MHz, the crystal
frequency is divided by 2 to obtain a Fdiv_ref of 20 MHz. Therefore:
Nfractional =Fvco_main
Fdiv_ref
= 902.4530
20
= 45.12265
The value to be programmed in the Main Divider Register is:
Nreg = Round[Nfractional] – 32
= Round[45.12265] – 32
= 45 – 32
= 13 (decimal)
=
000001101 (binary)
With the modulator in 18-bit mode, the value to be programmed in the Main Dividend Registers is:
dividend = Round[divider × (Nfractional – Nreg – 32)]
= Round[262144 × (45.12265 – 13 – 32)]
= Round[262144 × (0.12265)]
= Round[32151.9616]
= 32152 (decimal)
= 000111110110011000 (binary)
where 00 0111 1101 is loaded in the MSB of the Main Dividend Register and 1001 1000 is loaded in the LSB of the
Main Dividend Register.
Summary:
Main Divider Register = 0 0000 1101
Main Dividend LSB Register = 1001 1000
Main Dividend MSB Register = 00 0111 1101
The resulting main VCO frequency is 902.453 MHz
Step size is 76.3 Hz
Note: The frequency step size for this case is 20 MHz divided by 218, giving 76.3 Hz.
C1414
Figure 4. Fractional-N Applications: Sample Calculation (1 of 2)
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